数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

GS8342D19BD-350I 数据表(PDF) 9 Page - GSI Technology

部件名 GS8342D19BD-350I
功能描述  36Mb SigmaQuad-IITM Burst of 4 SRAM
Download  29 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  GSI [GSI Technology]
网页  http://www.gsitechnology.com
标志 GSI - GSI Technology

GS8342D19BD-350I 数据表(HTML) 9 Page - GSI Technology

Back Button GS8342D19BD-350I Datasheet HTML 5Page - GSI Technology GS8342D19BD-350I Datasheet HTML 6Page - GSI Technology GS8342D19BD-350I Datasheet HTML 7Page - GSI Technology GS8342D19BD-350I Datasheet HTML 8Page - GSI Technology GS8342D19BD-350I Datasheet HTML 9Page - GSI Technology GS8342D19BD-350I Datasheet HTML 10Page - GSI Technology GS8342D19BD-350I Datasheet HTML 11Page - GSI Technology GS8342D19BD-350I Datasheet HTML 12Page - GSI Technology GS8342D19BD-350I Datasheet HTML 13Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 29 page
background image
GS8342D07/10/19/37BD-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02a 8/2017
9/29
© 2011, GSI Technology
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175
 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K/K)
input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left
floating —the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination
is enabled. Termination impedance is programmed via the same RQ resistor (connected between the ZQ pin and VSS) used to
program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175
 and 250. Periodic
readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner
as for driver impedance (see above).
Note:
When ODT = 1, Data (D), Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, D, BW, K, K
inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the
input termination will pull the signal to VDDQ/2 (i.e., to the switch point of the diff-amp receiver), which could cause the receiver
to enter a meta-stable state and prevent the SRAM from operating within specification.
Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
A
R
W
Current
Operation
D
D
D
D
Q
Q
Q
Q
K
(tn-1)
K
(tn)
K
(tn)
K
(tn)
K
(tn)
K
(tn+1)
K
(tn+1½)
K
(tn+2)
K
(tn+2½)
K
(tn+2)
K
(tn+2½)
K
(tn+3)
K
(tn+3½)
Deselect
X
1
1
Deselect
X
X
Hi-Z
Hi-Z
Write
X
1
X
Deselect
D2
D3
Hi-Z
Hi-Z
Read
X
X
1
Deselect
X
X
Q2
Q3
Deselect
V
1
0
Write
D0
D1
D2
D3
Hi-Z
Hi-Z
Deselect
V
0
X
Read
X
X
Q0
Q1
Q2
Q3
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
Write
V
0
X
Read
D2
D3
Q0
Q1
Q2
Q3
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.


类似零件编号 - GS8342D19BD-350I

制造商部件名数据表功能描述
logo
GSI Technology
GS8342D19BD-300 GSI-GS8342D19BD-300 Datasheet
506Kb / 29P
   JEDEC-standard pinout and package
GS8342D19BD-300I GSI-GS8342D19BD-300I Datasheet
506Kb / 29P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342D19BD-333 GSI-GS8342D19BD-333 Datasheet
506Kb / 29P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
More results

类似说明 - GS8342D19BD-350I

制造商部件名数据表功能描述
logo
GSI Technology
GS8342D38BGD-350 GSI-GS8342D38BGD-350 Datasheet
523Kb / 30P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342D11BGD-350 GSI-GS8342D11BGD-350 Datasheet
523Kb / 30P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342DT11BD-550 GSI-GS8342DT11BD-550 Datasheet
524Kb / 30P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342DT38BD-400I GSI-GS8342DT38BD-400I Datasheet
524Kb / 30P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342D10BGD-450 GSI-GS8342D10BGD-450 Datasheet
506Kb / 29P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342D11BGD-550 GSI-GS8342D11BGD-550 Datasheet
523Kb / 30P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342D19BD-300I GSI-GS8342D19BD-300I Datasheet
506Kb / 29P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342D19BD-333 GSI-GS8342D19BD-333 Datasheet
506Kb / 29P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342D07BGD-350 GSI-GS8342D07BGD-350 Datasheet
506Kb / 29P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342DT10BD-333I GSI-GS8342DT10BD-333I Datasheet
507Kb / 29P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
GS8342DT07 GSI-GS8342DT07 Datasheet
467Kb / 29P
   36Mb SigmaQuad-IITM Burst of 4 SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com