GS8180QV18/36BD-200/167

Rev: 1.02b 11/2011

10/28

© 2007, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaQuad-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to

5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is

between 150

Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts

in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and

temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance

evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is

implemented with discrete binary weighted impedance steps.

Burst of 2 Coherency and Pass Through Functions

Because the Burst of 2 read and write commands are loaded at the same time, there may be some confusion over what constitutes

“coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately after a

write. This is true of the Burst of 2 except in one case, as is illustrated in the following diagram. If the user holds the same address

value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the Burst of 2 will

read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.

Burst of 2 Coherency and Pass Through Functions