数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

GS8662DT19BD-450 数据表(PDF) 7 Page - GSI Technology

部件名 GS8662DT19BD-450
功能描述  72Mb SigmaQuad-IITM Burst of 4 SRAM
Download  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  GSI [GSI Technology]
网页  http://www.gsitechnology.com
标志 GSI - GSI Technology

GS8662DT19BD-450 数据表(HTML) 7 Page - GSI Technology

Back Button GS8662DT19BD-450 Datasheet HTML 3Page - GSI Technology GS8662DT19BD-450 Datasheet HTML 4Page - GSI Technology GS8662DT19BD-450 Datasheet HTML 5Page - GSI Technology GS8662DT19BD-450 Datasheet HTML 6Page - GSI Technology GS8662DT19BD-450 Datasheet HTML 7Page - GSI Technology GS8662DT19BD-450 Datasheet HTML 8Page - GSI Technology GS8662DT19BD-450 Datasheet HTML 9Page - GSI Technology GS8662DT19BD-450 Datasheet HTML 10Page - GSI Technology GS8662DT19BD-450 Datasheet HTML 11Page - GSI Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 28 page
background image
GS8662DT07/10/19/37BD-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00b 8/2017
7/28
© 2011, GSI Technology
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are
needed. Therefore, the SigmaQuad-II+ SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O
SRAMs are unpopular in applications where multiple reads or multiple writes are needed because burst read or write transfers from
Separate I/O SRAMs can cut the RAM’s bandwidth in half.
SigmaQuad-II+ B4 SRAM DDR Read
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R high causes chip disable. A Low on
the Read Enable pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. Clocking
in a High on the Read Enable pin, R, begins a read port deselect cycle.
SRAM DDR Write
The status of the Address Input, W, and R pins are sampled by the rising edges of K. W and R High causes chip disable. A Low on
the Write Enable pin, W, and a High on the Read Enable pin, R, begins a write cycle. W is always ignored if the previous command
was a write command. Data is clocked in by the next rising edge of K, the rising edge of K after that, the next rising edge of K, and
finally by the next rising edge of K.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4-beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NWx” may be substituted in all the discussion above.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Beat 3
0
0
Data In
Data In
Beat 4
1
0
Don’t Care
Data In
Resulting Write Operation
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Byte 1
D0–D8
Byte 2
D9–D17
Written
Unchanged
Unchanged
Written
Written
Written
Unchanged
Written
Beat 1
Beat 2
Beat 3
Beat 4


类似零件编号 - GS8662DT19BD-450

制造商部件名数据表功能描述
logo
GSI Technology
GS8662DT19BD-450I GSI-GS8662DT19BD-450I Datasheet
505Kb / 28P
   JEDEC-standard pinout and package
More results

类似说明 - GS8662DT19BD-450

制造商部件名数据表功能描述
logo
GSI Technology
GS8662D19BD-300I GSI-GS8662D19BD-300I Datasheet
506Kb / 29P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662D07BD-350 GSI-GS8662D07BD-350 Datasheet
506Kb / 29P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662DT07BGD-400I GSI-GS8662DT07BGD-400I Datasheet
505Kb / 28P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662DT10BD-350I GSI-GS8662DT10BD-350I Datasheet
505Kb / 28P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662DT07 GSI-GS8662DT07 Datasheet
412Kb / 28P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662QT07 GSI-GS8662QT07 Datasheet
407Kb / 28P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662DT11BD-350 GSI-GS8662DT11BD-350 Datasheet
556Kb / 33P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662DT10BD-300I GSI-GS8662DT10BD-300I Datasheet
505Kb / 28P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662D07BD-450 GSI-GS8662D07BD-450 Datasheet
506Kb / 29P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662D20BGD-450 GSI-GS8662D20BGD-450 Datasheet
556Kb / 33P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
GS8662DT37BGD-400I GSI-GS8662DT37BGD-400I Datasheet
505Kb / 28P
   72Mb SigmaQuad-IITM Burst of 4 SRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com