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GS82583ED18GK-675I 数据表(PDF) 6 Page - GSI Technology |
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GS82583ED18GK-675I 数据表(HTML) 6 Page - GSI Technology |
6 / 26 page GS82583ED18/36GK-675/625/550/500 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.06 8/2017 6/26 © 2014, GSI Technology Power-Up and Reset Requirements For reliability purposes, power supplies must power up simultaneously, or in the following sequence: VSS, VDD, VDDQ, VREF and inputs. Power supplies must power down simultaneously, or in the reverse sequence. After power supplies power up, the following start-up sequence must be followed. Step 1 (Recommended, but not required): Assert RST High for at least 1ms. While RST is asserted high: • The DLL is disabled. • The states of R, and W control inputs are ignored. Note: If possible, RST should be asserted High before input clocks begin toggling, and remain asserted High until input clocks are stable and toggling within specification, in order to prevent unstable, out-of-spec input clocks from causing trouble in the SRAM. Step 2: Begin toggling input clocks. After input clocks begin toggling, but not necessarily within specification: • Q are placed in the non-Read state, and remain so until the first Read operation. • QVLD are driven Low, and remain so until the first Read operation. • CQ, CQ begin toggling, but not necessarily within specification. Step 3: Wait until input clocks are stable and toggling within specification. Step 4: De-assert RST Low (if asserted High). Step 5: Wait at least 160K (163,840) cycles. During this time: • Driver and ODT impedances are calibrated. Can take up to 160K cycles. Note: The DLL pin may be asserted High or de-asserted Low during this time. If asserted High, DLL synchronization begins immediately after the driver and ODT impedances are calibrated. If de-asserted Low, DLL synchronization begins after the DLL pin is asserted High (see Step 6). In either case, Step 7 must follow thereafter. Step 6: Assert DLL pin High (if de-asserted Low). Step 7: Wait at least 64K (65,536) cycles for the DLL to lock. After the DLL has locked: • CQ, CQ begin toggling within specification. Step 8: Begin initiating Read and Write operations. Reset Usage Although not generally recommended, RST may be asserted High at any time after completion of the initial power-up sequence described above, to reset the SRAM control logic to its initial power-on state. However, whenever RST is subsequently de-asserted Low (as in Step 4 above), Steps 5~7 above must be followed before Read and Write operations are initiated. Note: Memory array content may be perturbed/corrupted when RST is asserted High. |
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类似说明 - GS82583ED18GK-675I |
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