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GS81313LQ18GK-800 数据表(PDF) 4 Page - GSI Technology

部件名 GS81313LQ18GK-800
功能描述  144Mb SigmaQuad-IIIe Burst of 2 ECCRAM
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制造商  GSI [GSI Technology]
网页  http://www.gsitechnology.com
标志 GSI - GSI Technology

GS81313LQ18GK-800 数据表(HTML) 4 Page - GSI Technology

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GS81313LQ18/36GK-800/714/600
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.13 7/2016
4/26
© 2014, GSI Technology
Pin Description
Symbol
Description
Type
SA
Address — Read Address is registered on
CK and Write Address is registered on CK.
Input
D[35:0]
Write Data — Registered on
KD and KD during Write operations.
D[17:0] - x18 and x36.
D[35:18] - x36 only.
Input
Q[35:0]
Read Data — Aligned with
CQ and CQ during Read operations.
Q[17:0] - x18 and x36.
Q[35:18] - x36 only.
Output
QVLD[1:0]
Read Data Valid — Driven high one half cycle before valid Read Data.
Output
CK, CK
Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Input
KD[1:0],
KD[1:0]
Write Data Input Clocks — Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch Write Data (D[17:0] in x36, D[8:0] in x18).
KD1, KD1: latch Write Data (D[35:18] in x36, D[17:9] in x18).
Input
CQ[1:0],
CQ[1:0]
Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
CQ0, CQ0: align with Q[17:0] in x36, and Q[8:0] in x18.
CQ1, CQ1: align with Q[35:18] in x36, and Q[17:9] in x18.
Output
R
Read Enable — Registered on
CK. R = 0 initiates a Read operation.
Input
W
Write Enable — Registered on
CK. W = 0 initiates a Write operation.
Input
PLL
PLL Enable — Weakly pulled High internally.
PLL = 0: disables internal PLL.
PLL = 1: enables internal PLL.
Input
RST
Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Input
ZQ
Driver Impedance Control Resistor Input — Must be connected to VSS through an external resistor RQ to
program driver impedance.
Input
ZT
ODT Impedance Control Resistor Input — Must be connected to VSS through an external resistor RT to
program ODT impedance.
Input
RCS
Current Source Resistor Input — Must be connected to VSS through an external 2K resistor to provide
an accurate current source for the PLL.
Input
MZT[1:0]
ODT Mode Select — Set the ODT state globally for all input groups. Must be tied High or Low.
MZT[1:0] = 00: disables ODT on all input groups, regardless of PZT[1:0].
MZT[1:0] = 01: enables strong ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 10: enables weak ODT on select input groups, as specified by PZT[1:0].
MZT[1:0] = 11: reserved.
Input


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