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ST16C2552IJ44 数据表(PDF) 9 Page - Exar Corporation |
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ST16C2552IJ44 数据表(HTML) 9 Page - Exar Corporation |
9 / 28 page 3-143 ST16C2552 FCR BIT-1: 0=No change. 1=Clears the contents of the receive FIFO and resets its counter logic to 0 (the receive shift register is not cleared or altered). This bit will return to zero after clearing the FIFOs. FCR BIT-2: 0=No change. 1=Clears the contents of the transmit FIFO and resets its counter logic to 0 (the transmit shift register is not cleared or altered). This bit will return to zero after clearing the FIFOs. FCR BIT-3: 0=No change. 1=Changes RXRDY and TXRDY pins from mode “0” to mode “1”. Transmit operation in mode “0”: When ST16C2552 is in ST16C450 mode ( FCR bit- 0=0 ) or in the FIFO mode ( FCR bit-0=1, FCR bit-3=0 ) when there are no characters in the transmit FIFO or transmit holding register, the TXRDY* pin will go low. Once active the TXRDY* pin will go high (inactive) after the first character is loaded into the transmit holding register. Receive operation in mode “0”: When ST16C2552 is in ST16C450 mode ( FCR bit- 0=0 ) or in the FIFO mode ( FCR bit-0=1, FCR bit-3=0 ) and there is at least 1 character in the receive FIFO, the RXRDY* pin will go low. Once active the RXRDY* pin will go high (inactive) when there are no more characters in the receiver. Transmit operation in mode “1”: When ST16C2552 is in ST16C550 mode ( FCR bit- 0=1, FCR bit-3=1 ) the TXRDY* pin will become high (inactive) when the transmit FIFO is completely full. It will be low if one or more FIFO locations are empty. Receive operation in mode “1”: When ST16C2552 is in ST16C550 mode ( FCR bit- 0=1, FCR bit-3=1 ) and the trigger level or the timeout has been reached, the RXRDY* pin will go low. Once it is activated it will go high (inactive) when there are no more characters in the FIFO. FCR BIT 4-5: Not used. FCR BIT 6-7: These bits are used to set the trigger level for the receiver FIFO interrupt. BIT-7 BIT-6 FIFO trigger level 00 01 01 04 10 08 11 14 ALTERNATE FUNCTION REGISTER (AFR) This is a read/write register used to select specific modes of MF* operation and to allow both UART registers sets to be written concurrently. AFR BIT-0: When this bit is set, CPU can write concurrently to the same register in both UARTs. This function is intended to reduce the dual UART initialization time. It can be used by CPU when both channels are initialized to the same state. CPU can set or clear this bit by accessing either register set. When this bit is set the channel select pin still selects the channel to be accessed during read operation. Setting or clearing this bit has no effect on read operations. The user should ensure that LCR Bit-7 of both chan- nels are in the same state before executing a concur- rent write to the registers at address 0,1, or 2. AFR BIT 1-2: Combinations of these bits selects one of the MF* functions. |
类似零件编号 - ST16C2552IJ44 |
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类似说明 - ST16C2552IJ44 |
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