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GS81280Z18GT-250IV 数据表(PDF) 4 Page - GSI Technology |
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GS81280Z18GT-250IV 数据表(HTML) 4 Page - GSI Technology |
4 / 22 page TQFP Pin Descriptions Symbol Type Description A0, A1 In Burst Address Inputs; Preload the burst counter A In Address Inputs CK In Clock Input Signal BA In Byte Write signal for data inputs DQA1-DQA9; active low BB In Byte Write signal for data inputs DQB1-DQB9; active low BC In Byte Write signal for data inputs DQC1-DQC9; active low BD In Byte Write signal for data inputs DQD1-DQD9; active low W In Write Enable; active low E1 In Chip Enable; active low E2 In Chip Enable; Active High. For self decoded depth expansion E3 In Chip Enable; Active Low. For self decoded depth expansion G In Output Enable; active low ADV In Advance/Load; Burst address counter control pin CKE In Clock Input Buffer Enable; active low DQA I/O Byte A Data Input and Output pins DQB I/O Byte B Data Input and Output pins DQC I/O Byte C Data Input and Output pins DQD I/O Byte D Data Input and Output pins ZZ In Power down control; active high FT In Pipeline/Flow Through Mode Control; active low LBO In Linear Burst Order; active low VDD In Core power supply VSS In Ground VDDQ In Output driver power supply NC — No Connect NU — Not Used—There is an internal chip connection to these pins, but they are unused by the device. They may be left unconnected, tied Low (to VSS), or tied High (to VDDQ or VDD). GS81280Z18/36GT-xxxV Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.01 5/2017 4/21 © 2015, GSI Technology |
类似零件编号 - GS81280Z18GT-250IV |
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类似说明 - GS81280Z18GT-250IV |
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