GS4576C36GL-25I datasheet(8/63 Pages) GSI

部件名	GS4576C36GL-25I

功能描述	576Mb CIO Low Latency DRAM (LLDRAM II)

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制造商	GSI [GSI Technology]

网页	http://www.gsitechnology.com

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GS4576C09/18/36L

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.04 11/2013

8/62

Power–Up Initialization Sequence

200us Min

Mode Initialization

tMRSC

Refresh

1024 Cycles NOP Cycles Min

NOP

MRS

NOP

AREF

NOP

AC

CODE(1,2)

CODE(2)

ADDR

Bank 0

Bank 7

Valid

tDKL

tDK

tDKL

tDKH

tDK

tCKL

tCK

tCKL

tCKH

tCK

VEXT

VDD

VDDQ

VREF

VTT

CK

DK

Command

ADDR

BA

DM

DQ

All Banks(5)

Notes:

1.

Recommend all address pins held Low during dummy MRS commands.

2.

A10–A17 must be Low.

3.

DLL must be reset if tCK or VDD are changed.

4.

CK and CK must be separated at all times to prevent bogus commands from being issued.

5.

The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any operation,

tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.

类似零件编号 - GS4576C36GL-25I

制造商	部件名	数据表	功能描述
GSI Technology	GS4576C09	2Mb / 62P	64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)

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类似说明 - GS4576C36GL-25I

制造商	部件名	数据表	功能描述
GSI Technology	GS4576C09	2Mb / 62P	64M x 9, 32M x 18, 16M x 36 576Mb CIO Low Latency DRAM (LLDRAM II)
GSI Technology	GS4288C09	2Mb / 62P	32M x 9, 16M x 18, 8M x 36 288Mb CIO Low Latency DRAM (LLDRAM) II
Micron Technology	MT49H8M36	1Mb / 49P	288Mb CIO Reduced Latency
Renesas Technology Corp	UPD48576118F1	1Mb / 52P	576M-BIT Low Latency DRAM
	UPD48576209F1	1Mb / 54P	576M-BIT Low Latency DRAM
	UPD48288209AF1	1Mb / 54P	288M-BIT Low Latency DRAM
	UPD48288118AF1	1Mb / 52P	288M-BIT Low Latency DRAM
Micron Technology	MT49H8M32	652Kb / 43P	REDUCED LATENCY DRAM RLDRAM
Renesas Technology Corp	UPD48288209-A	862Kb / 50P	288M-BIT Low Latency DRAM Common I/O Feb 01, 2013
Renesas Technology Corp	UPD48288118-A	843Kb / 48P	288M-BIT Low Latency DRAM Separate I/O Feb 01, 2013