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HT86A36 数据表(PDF) 23 Page - Holtek Semiconductor Inc |
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HT86A36 数据表(HTML) 23 Page - Holtek Semiconductor Inc |
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23 / 68 page  HT86Axx/HT86ARxx Rev. 1.10 23 December 12, 2012 Look-up Table Registers - TBLP, TBHP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Pro- gram Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are ex- ecuted. Its value can be changed, for example using the ²INC² or ²DEC² instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user de- fined location. Watchdog Timer Register - WDTS The Watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a reset command when its value overflows. To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ra- tios, the value of which is set using the WDTS register. By writing directly to this register, the appropriate divi- sion ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set divi- sion ratios between 1 and 128. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system manage- ment flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, opera- tions related to the status register may give different re- sults due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the ²CLR WDT² or ²HALT² in- struction. The PDF flag is affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. · C is set if an operation results in a carry during an ad- dition operation or if a borrow does not take place dur- ing a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. · AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib- ble into the low nibble in subtraction; otherwise AC is cleared. · Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. · OV is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. · PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. · TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or execut- ing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Interrupt Control Register - INTC, INTCH Two 8-bit register, known as the INTC and INTCH regis- ters, controls the operation of both external and internal timer interrupts. By setting various bits within these reg- isters using standard bit manipulation instructions, the enable/disable function of the external and timer inter- rupts can be independently controlled. A master inter- rupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt en- able bits on or off. This bit is cleared when an interrupt T O P D F O V Z A C C S T A T U S R e g i s t e r A r i t h m e t i c / L o g i c O p e r a t i o n F l a g s C a r r y f l a g A u x i l i a r y c a r r y f l a g Z e r o f l a g O v e r f l o w f l a g S y s t e m M a n a g e m e n t F l a g s P o w e r d o w n f l a g W a t c h d o g t i m e - o u t f l a g N o t i m p l e m e n t e d , r e a d a s " 0 " b 7 b 0 Status Register |
类似零件编号 - HT86A36_12 |
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类似说明 - HT86A36_12 |
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