数据搜索系统,热门电子元器件搜索 |
|
HT82R732 数据表(PDF) 25 Page - Holtek Semiconductor Inc |
|
HT82R732 数据表(HTML) 25 Page - Holtek Semiconductor Inc |
25 / 74 page Wake-up Source Oscillator Type IRC External RES tRSDT +tSST1 PA, PB, PC Port tSST1 Interrupt WDT Overflow Note: 1. tRSTD (reset delay time), tSYS (system clock) 2. tRSTD is power-on delay, typical time=100ms 3. tSST1= 16 or 1024 tSYS, selected by the SSTC bit in the SYSC register. Wake-up Delay Time Watchdog Timer The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused by the program jumping to unknown locations due to certain uncontrollable external events such as electrical noise. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when the Watchdog Timer counter overflows. The Watchdog Timer clock can emanate from three different sources, selected by the WCS1 and WCS0 bits in the WDTC register. These are LXT, fSYS/4 or LIRC. It is important to note that when the system enters the HALT Mode the instruction clock is stopped, therefore if the WDTC register bits have selected fSYS/4 as the Watchdog Timer clock source, the Watchdog Timer will cease to function. For systems that operate in noisy environments, using the LIRC or the LXT as the clock source is therefore the recommended choice. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2. If the LIRC clock source is selected and with the WS0, WS1 and WS2 bits of the WDTS register all set high, the prescaler division ratio will be 1:128, which will give a maximum time-out period. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the HALT Mode, when a Watchdog Timer time-out occurs, the device will be woken up, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on the external reset pin. The second is using the Clear Watchdog Timer software instructions and the third is when a HALT instruction is executed. For a simple execution of ²CLR WDT² instruction will clear the Watchdog Timer. HT82R732 e-Banking 8-Bit OTP MCU Rev. 1.00 25 October 31, 2013 8 s t a g e c o u n t e r S / W O p t i o n W C S 1 , W C S 0 C L R W D T C L R f S Y S / 4 L I R C L X T f S 7 - b i t P r e s c a l e r 8 - t o - 1 M U X W S 0 ~ W S 2 C L R W D T T i m e - o u t Watchdog Timer |
类似零件编号 - HT82R732 |
|
类似说明 - HT82R732 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |