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HT82A525R 数据表(PDF) 19 Page - Holtek Semiconductor Inc |
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HT82A525R 数据表(HTML) 19 Page - Holtek Semiconductor Inc |
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19 / 71 page  The internal Timer/Event Counter 1 interrupt is initialized by setting the Timer/Event Counter 1 interrupt request flag (bit 6 of the INTC0), caused by a Timer 1 overflow. When the interrupt is enabled, the stack is not full and the T1F is set, a subroutine call to location 0CH will occur. The related interrupt request flag (T1F) will be reset and the EMI bit cleared to disable further interrupts. USB interrupts are triggered by the following USB events and the related interrupt request flag (USBF; bit 4 of the INTC1) will be set. · The access of the corresponding USB FIFO from PC · The USB suspend signal from the PC · The USB resume signal from the PC · USB reset signal Bit No. Label Function 0 EMI Global interrupt control (1: enable; 0: disable) 1 EEI External interrupt control (1: enable; 0: disable) 2 ET0I Timer/Event Counter 0 interrupt control (1: enable; 0: disable) 3 ET1I Timer/Event Counter 1 interrupt control (1: enable; 0: disable) 4 EIF External interrupt request flag (1: active; 0: inactive) 5 T0F Timer/Event Counter 0 interrupt request flag (1: active; 0: inactive) 6 T1F Timer/Event Counter 1 interrupt request flag (1: active; 0: inactive) 7 ¾ Unused bit, read as ²0² INTC0 (0BH) Register Bit No. Label Function 0 EUI USB interrupt control (1: enable; 0: disable) 1 ES1II Serial Interface 1 interrupt control (1: enable; 0: disable) 2 ES2II Serial Interface 2 interrupt control (1: enable; 0: disable) 3 ¾ Unused bit, read as ²0² 4 USBF USB interrupt request flag (1: active; 0: inactive) 5 SI1F Serial interface 1 interrupt request flag (1: active; 0: inactive) 6 SI2F Serial Interface 2 interrupt request flag (1: active; 0: inactive) 7 ¾ Unused bit, read as ²0² INTC1 (1EH) Register When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 10H will occur. The interrupt request flag (USBF) and EMI bits will be cleared to dis- able other interrupts. When PC Host access the FIFO of the HT82A525R, the corresponding request bit of USR is set, and a USB interrupt is triggered when the corresponding interrupt is enabled. So user can easily determine which FIFO is accessed. When the interrupt has been served, the corresponding bit should be cleared by firmware. When the HT82A525R receives a USB Suspend signal from the Host PC, the suspend line (bit0 of the USC) of the HT82A525R is set and a USB interrupt is also triggered. Also when the HT82A525R receives a Resume signal from the Host PC, the resume line (bit3 of the USC) of the HT82A525R is set and a USB interrupt is triggered. Rev. 1.80 19 March 11, 2016 HT82A525R I/O Type USB 8-Bit OTP MCU with SPI |
类似零件编号 - HT82A525R_16 |
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类似说明 - HT82A525R_16 |
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