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UPD48576209F1 数据表(PDF) 7 Page - Renesas Technology Corp |
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UPD48576209F1 数据表(HTML) 7 Page - Renesas Technology Corp |
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7 / 54 page  µµµµPD48576209F1, µµµµPD48576218F1, µµµµPD48576236F1 R10DS0256EJ0101 Rev. 1.01 Page 7 of 53 Jan. 15, 2016 (2/2) Symbol Type Description ZQ Input /Output External impedance [25 Ω – 60 Ω]; This signal is used to tune the device outputs to the system data bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this signal to VSS. Connecting ZQ to VSS invokes the minimum impedance mode. Connecting ZQ to VDDQ invokes the maximum impedance mode. Refer to Figure 2-5. Mode Register Bit Map to activate this function. TMS , TDI Input JTAG function pins: IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used in the circuit TCK Input JTAG function pin; IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used in the circuit. TDO Output JTAG function pin; IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if JTAG function is not used. VREF Input Input reference voltage; Nominally VDDQ/2. Provides a reference voltage for the input buffers. VEXT Supply Power supply; 2.5 V nominal. See Recommended DC Operating Conditions for range. VDD Supply Power supply; 1.8 V nominal. See Recommended DC Operating Conditions for range. VDDQ Supply DQ power supply; Nominally, 1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See Recommended DC Operating Conditions for range. VSS Supply Ground VSSQ Supply DQ ground; Isolated on the device for improved noise immunity. VTT Supply Power supply; Isolated termination supply. Nominally, VDDQ/2. See Recommended DC Operating Conditions for range. NF No function; These balls may be connected to VSS. DNU Do not use; These balls may be connected to VSS. |
类似零件编号 - UPD48576209F1 |
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类似说明 - UPD48576209F1 |
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