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UPD48576118F1 数据表(PDF) 17 Page - Renesas Technology Corp |
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UPD48576118F1 数据表(HTML) 17 Page - Renesas Technology Corp |
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17 / 52 page  µµµµPD48576118F1 R10DS0257EJ0101 Rev. 1.01 Page 17 of 51 Jan. 15, 2016 2.4 Power-On Sequence Figure 2-1. Power-Up Sequence Notes 1. Recommended all address pins held LOW during dummy MRS commands. 2. A10-A17 must be LOW. Remark MRS : MRS command RFp : REFRESH bank p AC : Any command 2.5 Programmable Impedance Output Buffer The µPD48576118F1 is equipped with programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ ball and VSS. The value of the resistor must be five times the desired impedance. For example, a 300 Ω resistor is required for an output impedance of 60 Ω. To ensure that output impedance is one fifth the value of RQ (within 15 percent), the range of RQ is 125 Ω to 300 Ω. Output impedance updates may be required because, over time, variations may occur in supply voltage and temperature. The device samples the value of RQ. An impedance update is transparent to the system and does not affect device operation. All data sheet timing and current specifications are met during an update. 2.6 PLL Reset The µPD48576118F1 utilizes internal Phase-locked loops for maximum output, data valid windows. It can be placed into a stopped-clock state to minimize power with a modest restart time of 15 µs. The clock (CK/CK#) must be toggled for 15 µs in order to stabilize PLL circuits for next READ operation. 2.7 Clock Input Table 2-3. Clock Input Operation Conditions Parameter Symbol Conditions MIN. MAX. Unit Note Clock Input Voltage Level VIN (DC) CK and CK# -0.3 VDDQ + 0.3 V Clock Input Differential Voltage Level VID (DC) CK and CK# 0.2 VDDQ + 0.6 V 8 Clock Input Differential Voltage Level VID (AC) CK and CK# 0.4 VDDQ + 0.6 V 8 Clock Input Crossing Point Voltage Level VIX (AC) CK and CK# VDDQ/2 - 0.15 VDDQ/2 + 0.15 V 9 VEXT VDD VDDQ VREF CK# CK COMMAND 200µs MIN. tMRSC tRC Refresh all banks MRS MRS MRS RF0 RF1 RF7 AC ADDRESS VTT NOP NOP NOP Don't care A 15µs A A Note 1, 2 Note 1, 2 Note 2 |
类似零件编号 - UPD48576118F1 |
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类似说明 - UPD48576118F1 |
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