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UPD48288118AF1 数据表(PDF) 16 Page - Renesas Technology Corp |
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UPD48288118AF1 数据表(HTML) 16 Page - Renesas Technology Corp |
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16 / 52 page  µµµµPD48288118AF1 R10DS0255EJ0101 Rev. 1.01 Page 16 of 51 Jan. 15, 2016 AREF The AREF is used during normal operation of the µPD48288118AF1 to refresh the memory content of a bank. The command is non-persistent, so it must be issued each time a refresh is required. The value on the BA0–BA2 inputs selects the bank. The refresh address is generated by an internal refresh controller, effectively making each address bit a “Don’t Care” during the AREF command. The µPD48288118AF1 requires 64K cycles at an average periodic interval of 0.49µs Note2 (MAX.). To improve efficiency, eight AREF commands (one for each bank) can be posted to µPD48288118AF1 at periodic intervals of 3.9 µs Note3. Within a period of 32 ms, the entire memory must be refreshed. The delay between the AREF command and a subsequent command to same bank must be at least tRC as continuous refresh. Other refresh strategies, such as burst refresh, are also possible. Notes 1. When the chip is deselected, internal NOP commands are generated and no commands are accepted. 2. Actual refresh is 32 ms / 8k / 8 = 0.488 µs. 3. Actual refresh is 32 ms / 8k = 3.90 µs. 2.3 Initialization The µPD48288118AF1 must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operations or permanent damage to the device. The following sequence is used for Power-Up: 1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) and start clock as soon as the supply voltages are stable. Apply VDD and VEXT before or at the same time as VDDQ. Apply VDDQ before or at the same time as VREF and VTT. Although there is no timing relation between VEXT and VDD, the chip starts the power-up sequence only after both voltages are at their nominal levels. VDDQ supply must not be applied before VDD supply. CK/CK# must meet VID(DC) prior to being applied. Maintain all remaining balls in NOP conditions. Note No rule of apply power sequence is the design target. 2. Maintain stable conditions for 200 µs (MIN.). 3. Issue at least three or more consecutive MRS commands: two dummies or more plus one valid MRS. It is recommended that all address pins are held LOW during the dummy MRS commands. 4. tMRSC after valid MRS, an AUTO REFRESH command to all 8 banks must be issued and wait for 15 µs with CK/CK# toggling in order to lock the PLL prior to normal operation. 5. After tRC, the chip is ready for normal operation. |
类似零件编号 - UPD48288118AF1 |
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类似说明 - UPD48288118AF1 |
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