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S5D9 数据表(PDF) 95 Page - Renesas Technology Corp

部件名 S5D9
功能描述  Microcontroller
Download  115 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

S5D9 数据表(HTML) 95 Page - Renesas Technology Corp

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R01DS0303EU0100 Rev.1.00
Page 95 of 115
Nov 3, 2016
S5D9
2. Electrical Characteristics
Figure 2.92
Oscillation stop detection timing
2.9
POR and LVD Characteristics
Note 1.
The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection levels VPOR,
Vdet1, and Vdet2 for POR and LVD.
Note 2.
The low-power function is disabled and DEEPCUT[1:0] = 00b or 01b.
Note 3.
The low-power function is enabled and DEEPCUT[1:0] = 11b.
Table 2.47
Power-on reset circuit and voltage detection circuit characteristics
Item
Symbol
Min
Typ
Max
Unit
Test conditions
Voltage detection
level
Power-on reset
(POR)
Module-stop function
disabled*2
VPOR
2.5
2.6
2.7
V
Figure 2.93
Module-stop function
enabled*3
1.8
2.25
2.7
Voltage detection circuit (LVD0)
Vdet0_1
2.84
2.94
3.04
Figure 2.94
Vdet0_2
2.77
2.87
2.97
Vdet0_3
2.70
2.80
2.90
Voltage detection circuit (LVD1)
Vdet1_1
2.89
2.99
3.09
Figure 2.95
Vdet1_2
2.82
2.92
3.02
Vdet1_3
2.75
2.85
2.95
Voltage detection circuit (LVD2)
Vdet2_1
2.89
2.99
3.09
Figure 2.96
Vdet2_2
2.82
2.92
3.02
Vdet2_3
2.75
2.85
2.95
Internal reset time
Power-on reset time
tPOR
-4.5
-
ms
Figure 2.93
LVD0 reset time
tLVD0
-0.51
-
Figure 2.94
LVD1 reset time
tLVD1
-0.38
-
Figure 2.95
LVD2 reset time
tLVD2
-0.38
-
Figure 2.96
Minimum VCC down time*1
tVOFF
200
-
-
μs
Figure 2.93,
Figure 2.94
Response delay
tdet
-
-
200
μs
Figure 2.93 to
Figure 2.96
LVD operation stabilization time (after LVD is enabled)
td(E-A)
--
10
μs
Figure 2.95,
Figure 2.96
Hysteresis width (LVD1 and LVD2)
VLVH
-70
-
mV
tdr
Main clock
OSTDSR.OSTDF
MOCO clock
ICLK


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