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S5D9 数据表(PDF) 73 Page - Renesas Technology Corp |
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S5D9 数据表(HTML) 73 Page - Renesas Technology Corp |
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73 / 115 page  R01DS0303EU0100 Rev.1.00 Page 73 of 115 Nov 3, 2016 S5D9 2. Electrical Characteristics Figure 2.55 Transmit and receive timing 2.3.13 IIC Timing Table 2.27 IIC timing (1) (1 of 2) (1) Conditions: Middle drive output is selected in the port drive capability bit in the PmnPFS register for the following pins: SDA0_B, SCL0_B, SDA1_A, SCL1_A, SDA1_B, SCL1_B. (2) The following pins do not require setting: SCL0_A, SDA0_A, SCL2, SDA2. (3) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the AC portion of the electrical characteristics is measured for each group. Item Symbol Min*1 Max Unit Test conditions*3 IIC (Standard mode, SMBus) ICFER.FMPE = 0 SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 - ns Figure 2.56 SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 - ns SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns SCL, SDA input rise time tSr - 1000 ns SCL, SDA input fall time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 0 1 (4) × tIICcyc ns SDA input bus free time when wakeup function is disabled tBUF 3 (6) × tIICcyc + 300 - ns SDA input bus free time when wakeup function is enabled tBUF 3 (6) × tIICcyc + 4 × tPcyc + 300 -ns START condition input hold time when wakeup function is disabled tSTAH tIICcyc + 300 - ns START condition input hold time when wakeup function is enabled tSTAH 1 (5) × tIICcyc + tPcyc + 300 -ns Repeated START condition input setup time tSTAS 1000 - ns STOP condition input setup time tSTOS 1000 - ns Data input setup time tSDAS tIICcyc + 50 - ns Data input hold time tSDAH 0- ns SCL, SDA capacitive load Cb - 400 pF tSU tH tLEAD tTD tLAG tOH tOD MSB IN DATA LSB IN MSB OUT DATA LSB OUT IDLE QSSL output QSPCLK output QIO0-3 input QIO0-3 output |
类似零件编号 - S5D9 |
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类似说明 - S5D9 |
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