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ACE24AC128 数据表(PDF) 4 Page - ACE Technology Co., LTD. |
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ACE24AC128 数据表(HTML) 4 Page - ACE Technology Co., LTD. |
4 / 16 page ACE24AC128 Two-wire Serial EEPROM VER 1.1 4 Memory Organization The ACE24AC128 devices have 256 pages respectively. Since each page has 64 bytes, random word addressing to ACE24AC128 will require 14 bits data word addresses respectively. Device Operation (A) Serial Clock And Data Transitions The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a start or stop condition as described below. (B) Start Condition With SCL VIH, a SDA transition from high to low is interpreted as a start condition. All valid commands must begin with a start condition. (C) Stop Condition With SCL VIH, a SDA transition from low to high is interpreted as a stop condition. All valid read or write commands end with a stop condition. The device goes into the standby mode if it is after a read command. A stop condition after page or byte write command will trigger the chip into the standby mode after the self-timed internal programming finish (see Figure 1). (D) Acknowledge The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The acknowledge signal occurs on the 9 th serial clock after each word. (E) Standby Mode The EEPROM goes into low power standby mode after a fresh power up, after receiving a stop bit in read mode, or after completing a self-time internal programming operation. Figure 1: Timing diagram for start and stop conditions |
类似零件编号 - ACE24AC128 |
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类似说明 - ACE24AC128 |
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