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TSEV8388BF 数据表(PDF) 5 Page - ATMEL Corporation |
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TSEV8388BF 数据表(HTML) 5 Page - ATMEL Corporation |
5 / 57 page 5 TS8388B 2144C–BDC–04/03 Positive supply current Analog Digital I CC IPLUSD 1, 2 6 1, 2 6 – – – – 385 395 115 120 445 445 145 145 mA mA mA mA Negative supply voltage VEE 1, 2, 6 -5.3 -5 -4.7 V Negative supply current Analog Digital AIEE DIEE 1, 2 6 1, 2 6 – – – – 165 170 135 145 200 200 180 180 mA mA mA mA Nominal power dissipation PD 1, 2 6 – – 3.4 3.6 4.1 4.3 W W Power supply rejection ratio PSRR 4 – 0.5 2 mW Resolution – – – 8 – bits (2) Analog Inputs Full Scale Input Voltage range (differential mode) (0V common mode voltage) VIN VINB 4 – -125 -125 – – 125 125 mV mV Full Scale Input Voltage range (single-ended input option) (See Application Notes) V IN VINB 4 – -250 – – 0 250 – mV mV Analog input capacitance C IN 4– 3 3.5 pF Input bias current I IN 4 – 10 20 µA Input Resistance RIN 40.5 1 – M Ω Full Power input Bandwidth (-3dB) CBGA68 package CQFP68 package FPBW – – – 4 4 – – – – 1.8 1.5 – – – – GHz GHz – Small signal input Bandwidth (10% full scale) SSBW 4 1.5 1.7 – GHz Clock Inputs Logic compatibility for clock inputs (See Application Notes) –– ECL or specified clock input power level in dBm – (10) ECL Clock inputs voltages (V CLK or VCLKB): – 4 ––– – Logic “0” voltage VIL –– – -1.5 V Logic “1” voltage V IH –-1.1 – – V Logic “0” current I IL –– 5 50 µA Logic “1” current IIH –– 5 50 µA Clock input power level into 50 Ω termination – – dBm into 50 Ω – Clock input power level – 4 -2 4 10 dBm Clock input capacitance CCLK 4– 3 3.5 pF Table 3. Electrical Specifications (Continued) Parameter Symbol Test Level Value Unit Note Min Typ Max |
类似零件编号 - TSEV8388BF |
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类似说明 - TSEV8388BF |
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