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AD7771 数据表(PDF) 8 Page - Analog Devices |
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AD7771 数据表(HTML) 8 Page - Analog Devices |
8 / 14 page Rev. PrC | Page 7 of 13 Parameter Test Conditions Comment Min Typ Max Unit 2.3V≤ IOVDD ≤3.6V 0.7× IOVDD V Input Low Voltage, VINL 1.65V≤ IOVDD ≤1.95V 0.35× IOVDD V 2.3V≤ IOVDD ≤3.6V 0.4 V Hysteresis2 0.2 % IOVDD <2.7V 0.1 % Input Currents -10 +10 µA LOGIC OUTPUT (DOUT/RDY, DCLK, SDOUT, GPIO) Output High Voltage, VOH IOVDD ≥ 3V, ISOURCE = 1mA 0.8× IOVDD V 2.3≤IOVDD< 3V, ISOURCE 500μA 0.8× IOVDD V IOVDD <2.3V, ISOURCE = 200μA 0.8× IOVDD V Output Low Voltage, VOL IOVDD ≥3V, ISINK 2mA 0.4 V 2.3≤IOVDD <3V, ISINK 1mA 0.4 V IOVDD < 2.3V, ISINK 100μA 0.4 V Leakage Current Floating State -10 +10 µA Output Capacitance Floating State 10 pF ΣΔ Data Output Coding 2s Comp SAR Data Output Coding Binary POWER SUPPLIES All ΣΔ Channels Enabled CMOS clock, AVDD1x/AVDD2x/AVDD4 = 3.3v, IOVDD = 1.8v AVDD1x − AVSS 3.0 3.6 V I_AVDD1x12 Reference Buffer Pre-Q , VCM Enable, Internal reference Enable HR 17 LP 4.5 mA Reference Buffer Enable, VCM Enabled, Internal reference Enabled mA HR 19 LP 5 mA Reference Buffer Disable, VCM disabled, Internal reference Disabled mA HR 13 LP 3.5 mA AVDD2 – AVSS 2.2 3.6 V I_AVDD2x HR 9 mA LP 3.5 mA AVDD4 – AVSS4 AVDD1x 3.6 IAVDD4 SAR enable, 256ksps 1.6 mA SAR disable 0.05 uA AVSS-DGND -1.8 0 V Preliminary Technical Data AD7771 |
类似零件编号 - AD7771 |
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类似说明 - AD7771 |
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