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CAT25020V 数据表(PDF) 9 Page - Catalyst Semiconductor |
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CAT25020V 数据表(HTML) 9 Page - Catalyst Semiconductor |
9 / 11 page 9 CAT25010/20/40 Doc. No. 1006, Rev. L Figure 9. HOLD HOLD HOLD HOLD HOLD Timing DESIGN CONSIDERATIONS The CAT250140/20/40 powers up in a write disable state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write, the CAT250140/20/40 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and programming is continued. On power up, Figure 8. Page Write Instruction Timing Note: Dashed Line= mode (1, 1) – –––– *X=0 for 25010, 25020 ; X=A8 for 25040 Note: Dashed Line= mode (1, 1) – –––– CS SCK HOLD SO tCD tHD tHD tCD tLZ tHZ HIGH IMPEDANCE SO is in a high impedance. If an invalid op code is received, no data will be shifted into the CAT250140/ 20/40, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. When powering down, the supply should be taken down to 0V, so that the CAT250140/20/40 will be reset when power is ramped back up. If this is not possible, then, following a brown-out episode, the CAT250140/20/40 can be reset by refreshing the contents of the Status Register (See Application Note AN10). SK SI SO 00 00 00 10 BYTE ADDRESS Data Byte 1 012345678 13 14 15 16-23 24-31 Data Byte 2 Data Byte 3 Data Byte N CS OPCODE 7..1 0 16+(N-1)x8-1..16+(N-1)x8 16+Nx8-1 DATA IN HIGH IMPEDANCE A7 A0 X* |
类似零件编号 - CAT25020V |
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类似说明 - CAT25020V |
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