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TPD4E001-Q1 数据表(PDF) 9 Page - Texas Instruments |
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TPD4E001-Q1 数据表(HTML) 9 Page - Texas Instruments |
9 / 28 page IO3 IO4 GND IO2 IO1 0.1µF V CC USB Controller R T V BUS D+ D– GND V BUS D+ D– GND D1 9 TPD4E001 www.ti.com SLLS682L – JULY 2006 – REVISED MAY 2016 Product Folder Links: TPD4E001 Submit Documentation Feedback Copyright © 2006–2016, Texas Instruments Incorporated 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPD4E001 is a diode array type Transient Voltage Suppressor (TVS) which is typically used to provide a path to ground for dissipating ESD events on hi-speed signal lines between a human interface connector and a system. As the current from ESD passes through the TVS, only a small voltage drop is present across the diode. This is the voltage presented to the protected IC. The low RDYN of the triggered TVS holds this voltage, VCLAMP, to a tolerable level to the protected IC. 8.2 Typical Application Figure 4. Typical Application Schematic 8.2.1 Design Requirements For this design example, a single TPD4E001 is used to protect all the pins of two USB2.0 connectors. Given the USB application, the following parameters are known. Table 1. Design Parameters DESIGN PARAMETER VALUE Signal range on IO1, IO2, IO3, and IO4 0 V to 3.6 V Signal voltage range on VCC 0 V to 5.25 V Operating Frequency 240 MHz 8.2.2 Detailed Design Procedure When placed near the USB connectors, the TPD4E001 ESD solution offers little or no signal distortion during normal operation due to low IO capacitance and ultra-low leakage current specifications. The TPD4E001 ensures that the core circuitry is protected and the system is functioning properly in the event of an ESD strike. For proper operation, the following layout/ design guidelines should be followed: 1. Place the TPD4E001 solution close to the connectors. This allows the TPD4E001 to take away the energy associated with ESD strike before it reaches the internal circuitry of the system board. 2. Place a 0.1- μF capacitor very close to the VCC pin. This limits any momentary voltage surge at the IO pin during the ESD strike event. |
类似零件编号 - TPD4E001-Q1 |
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类似说明 - TPD4E001-Q1 |
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