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TP3155 数据表(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 TP3155
功能描述  TP3155 Time Slot Assignment Circuit
Download  10 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

TP3155 数据表(HTML) 6 Page - National Semiconductor (TI)

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Definitions and Timing Conventions
DEFINITIONS
VIH
VIH is the dc input level above which
an input level is guaranteed to appear
as a logical one This parameter is to
be measured by performing a function-
al test at reduced clock speeds and
nominal timing (ie not minimum setup
and hold times or output strobes) with
the high level of all driving signals set
to VIH and maximum supply voltages
applied to the device
VIL
VIL is the dc input level below which
an input level is guaranteed to appear
as a logical zero to the device This pa-
rameter is measured in the same man-
ner as VIH but with all driving signal low
levels set to VIL and minimum supply
voltages applied to the device
VOH
VOH is the minimum dc output level to
which an output placed in a logical one
state will converge when loaded at the
maximum specified load current
VOL
VOL is the maximum dc output level to
which an output placed in a logical zero
state will converge when loaded at the
maximum specified load current
Threshold Region
The threshold region is the range of in-
put voltages between VIL and VIH
Valid Signal
A signal is Valid if it is in one of the valid
logic states (ie above VIH or below
VIL) In timing specifications a signal is
deemed valid at the instant it enters a
valid state
Invalid Signal
A signal is Invalid if it is not in a valid
logic state ie when it is in the thresh-
old region between VIL and VIH In tim-
ing specifications a signal is deemed
Invalid at the instant it enters the
threshold region
TIMING CONVENTIONS
For the purposes of this timing specification the following
conventions apply
Input Signals
All input signals may be characterized
as VL e 04V VH e 24V tR k 10 ns
tF k 10ns
Period
The period of clock signal is designated
as tPxx where xx represents the mne-
monic of the clock signal being speci-
fied
Rise Time
Rise times are designated as tRyy
where yy represents a mnemonic of the
signal whose rise time is being speci-
fied tRyy is measured from VIL to VIH
Fall Time
Fall times are designated as tFyy
where yy represents a mnemonic of the
signal whose fall time is being speci-
fied tFyy is measured from VIH to VIL
Pulse Width High
The high pulse width is designated as
tWzzH where zz represents the mne-
monic of the input or output signal
whose pulse width is being specified
High pulse widths are measured from
VIH to VIH
Pulse Width Low
The low pulse width is designated as
tWzzL where zz represents the mne-
monic of the input or output signal
whose pulse width is being specified
Low pulse widths are measured from
VIL to VIL
Setup Time
Setup times are designated as tSwwxx
where ww represents the mnemonic of
the input signal whose setup time is be-
ing specified relative to a clock or
strobe input represented by mnemonic
xx Setup times are measured from the
ww Valid to xx Invalid
Hold Time
Hold times are designated as tHxxww
where ww represents the mnemonic of
the input signal whose hold time is be-
ing specified relative to a clock or
strobe input represented by mnemonic
xx Hold times are measured from xx
Valid to ww Invalid
Delay Time
Delay
times
are
designated
as
tDxxyy lHlL where xx represents the
mnemonic of the input reference signal
and yy represents the mnemonic of the
output signal whose timing is being
specified relative to xx The mnemonic
may optionally be terminated by an H
or L to specify the high going or low
going transition of the output signal
Maximum delay times are measured
from xx Valid to yy Valid Minimum de-
lay times are measured from xx Valid to
yy Invalid This parameter is tested un-
der the load conditions specified in the
Conditions column of the Timing Speci-
fications section of this data sheet
6


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