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AM24LC21BISA 数据表(PDF) 10 Page - List of Unclassifed Manufacturers |
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AM24LC21BISA 数据表(HTML) 10 Page - List of Unclassifed Manufacturers |
10 / 13 page AM24LC21B Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM (Preliminary) Anachip Corp. www.anachip.com.tw Rev 0.1 Jul 2, 2003 10/13 Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Next Operation Die Device Acknowledg (ACK = 0)? YES No Figure 5-1: Acknowledge polling flow 7.0 Read operation Read operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 7.1 Current address read The AM24LC21B contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to ‘1’, the AM24LC21B issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the AM24LC21B discontinues transmission (Figure 7-1). 7.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the AM24LC21B as part of a write operation. After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a ‘1’. The AM24LC21B will then issue an acknowledge and transmits the eight bit data word.The master will not acknowledge the transfer but does generate a stop condition and the AM24LC21B discontinues transmission (Figure 7-2). 7.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the AM24LC21B transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. This directs the AM24LC21B to transmit the next sequentially addressed 8-bit word (see Figure 7-3). To provide sequential reads the AM24LC21B contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. 7.4 Noise protection The AM24LC21B employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. P S T O P N O A C K A C K S S T A R T Control Byte Data(n) Bus activity SDA Line Bus activity Master |
类似零件编号 - AM24LC21BISA |
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类似说明 - AM24LC21BISA |
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