Si5017-EVB

Rev. 1.0

3

Figure 1. LOS_LVL Mapping

Extended LOS Hysteresis Option

An optional LOS Hysteresis Extension circuit is included

on the Si5017-EVB to provide a convenient means of

increasing the amount of LOS Alarm hysteresis when

testing and evaluating the Si5017 LOS functionality.

This simple network will extend the LOS hysteresis to

approximately 6 dB, thereby preventing unnecessary

switching on LOS for low level DATAIN signals in the

the LOS deassert level (LOSD) and the LOS assert

level (LOSA). The hysteresis in decibels is calculated as

20log(LOSD/LOSA). This circuit is constructed with one

CMOS inverter (U2) and two resistors (R12, R13)

mounted on the underside of the PCB. If desired, this

circuit can be enabled by installing a jumper on JP17

(HYST ENABLE) located near the power entry block.

Data Slicing Level

The slicing level allows optimization of the input cross-

over point for systems where the slicing level is not at

the amplitude average. The data slicing level can be

adjusted from the nominal cross-over point of the data

by applying a voltage to the SLICE_LVL pin.

SLICE_LVL is controllable through the BNC jack J11.

The SLICE_LVL to the data slicing level is mapped as

follows:

If this function is not used, jumper JP6.

Bit-Error-Rate Alarm Threshold

The bit-error-rate of the incoming data can be monitored

by the BER_ALM pin. When the bit-error-rate exceeds

an externally set threshold level, BER_ALM is asserted.

BER_ALM is brought to a test point located in the upper

right-hand corner of the board. The BER_ALM threshold

level is set by applying a dc voltage to the BER_LVL pin.

BER_LVL is controllable through the BNC jack J12.

Jumper JP7 to disable the BER alarm. Refer to the

“BER Detection” section of the Si5016/Si5017 data

sheet for threshold level programming.

Test Configuration

The three critical jitter tests typically performed on a

CDR device are jitter transfer, jitter tolerance, and jitter

generation. By connecting the Si5017 Evaluation Board

as shown in Figure 2, all three measurements can be

easily made.

When applied, REFCLK should be within ±100 ppm of

the frequency selected from Table 1 and RESET/CAL

must be unjumpered.

Jitter Tolerance: Referring to Figure 2, this test

requires

a

pattern

generator,

a

clock

source

(synthesizer signal source), a modulation source, a jitter

analyzer, a pattern analyzer, and a pulse generator (all

unconnected high-speed outputs must be terminated to

50

Ω). During this test, the Jitter Analyzer directs the

Modulation Source to apply prescribed amounts of jitter

to the synthesizer source. This “jitters” the pattern

generator timebase which drives the DATAIN ports of

the CDR. The Bit-Error-Rate (BER) is monitored on the

Pattern Analyzer. The modulation (jitter) frequency and

amplitude is recorded when the BER approaches a

specified threshold. The Si5017 limiting amplifier can

also be examined during this test. Simply lower the

amplitude of the incoming data to the minimum value

typically expected at the limiting amplifier inputs

Jitter Generation: Referring to Figure 2, this test

requires

a

pattern

generator,

a

clock

source

(synthesizer signal source), a jitter analyzer, and a

pulse generator (all unconnected high-speed outputs

must be terminated to 50

Ω). During this test, there is no

modulation of the Data Clock, so the data that is sent to

the CDR is jitter free. The Jitter Analyzer measures the

RMS and peak-to-peak jitter on the CDR CLKOUT.

Thus, any jitter measured is jitter generated by the

CDR.

Jitter Transfer: Referring to Figure 2, this test requires

a pattern generator, a clock source (synthesizer signal

source), a modulation source, a jitter analyzer, and a

pulse generator (all unconnected high-speed outputs

must be terminated to 50

Ω). During this test, the Jitter

Analyzer modulates the data pattern and data clock

reference. The modulated data clock reference is

compared with the CLKOUT of the CDR. Jitter on

CLKOUT relative to the jitter on the data clock reference

is plotted versus modulation frequency at predefined

jitter amplitudes.

40 mV/V

0 mV

0 V

LOS_LVL (V)

30 mV

2.25 V

1.50 V

1.00 V

15 mV

1.875 V

40 mV

2.5 V

–

50

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