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SI4322 数据表(PDF) 10 Page - Silicon Laboratories |
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SI4322 数据表(HTML) 10 Page - Silicon Laboratories |
10 / 22 page Si4322 10 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 1 0 0 0 0 0 0 d1 d0 g1 g0 r2 r1 r0 en C080h d1 d0 VDI output 0 0 Digital RSSI Out (DRSSI) 0 1 Data Quality Detector Output (DQD) 1 0 Clock recovery lock 1 1 Always g1 g0 GLNA (dB relative to max. G) 0 0 0 0 1 -6 1 0 -12 1 1 -18 r2 r1 r0 RSSIsetth [dBm] 0 0 0 -103 0 0 1 -97 0 1 0 -91 0 1 1 -85 1 0 0 -79 1 0 1 -73 1 1 0 -67 1 1 1 -61 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 1 0 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 f0 AD57h Band [MHz] C 868 10 915 11 Frequency Setting Command Receiver Setting Command The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated: RSSI th = RSSIsetth + GLNA Bit 0 <en>: Enables the whole receiver chain and crystal ocsillator when set. Enable/disable of the wake-up timer and the low battery detector are not affected by this setting. Bit 7-6 <d1:d0>: Select the VDI (valid data indicator) signal: Bit 5-4 <g1:g0>: Set the LNA gain: The 12-bit Frequency Setting Command <f11 : f0> has the value F. The value F should be in the range of 96 and 3903. When F is out of range, the previous value is kept. The synthesizer center frequency f 0 can be calculated as: f 0 = 8 * 10 MHz * (C + F/4000) The constant C is determined by the selected band as: Bit 3-1 <r2:r0>: Control the threshold of the RSSI detector: |
类似零件编号 - SI4322 |
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类似说明 - SI4322 |
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