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ADF4211 数据表(PDF) 1 Page - Analog Devices

部件名 ADF4211
功能描述  Dual RF/IF PLL Frequency Synthesizers
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADF4211 数据表(HTML) 1 Page - Analog Devices

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REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
ADF4210/ADF4211/ADF4212/ADF4213
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
Dual RF/IF PLL Frequency Synthesizers
FUNCTIONAL BLOCK DIAGRAM
OSCILLATOR
CLOCK
DATA
LE
24-BIT
DATA
REGISTER
IF
LOCK
DETECT
MUXOUT
ADF4210/ADF4211/
ADF4212/ADF4213
CPRF
CPIF
PHASE
COMPARATOR
OUTPUT
MUX
14-BIT IF
R-COUNTER
REFIN
RF
PRESCALER
RFIN
PHASE
COMPARATOR
14-BIT RF
R-COUNTER
12-BIT RF
B-COUNTER
6-BIT RF
A-COUNTER
VDD1VDD2VP1VP2
AGNDRF
DGNDRF
DGNDIF
AGNDIF
RF
LOCK
DETECT
SDOUT
DGNDIF
IF
PRESCALER
IFIN
8-BIT IF
A-COUNTER
CHARGE
PUMP
IF CURRENT
SETTING
REFERENCE
RFCP3 RFCP2 RFCP1
RSET
FLO SWITCH
FLO
IF CURRENT
SETTING
IFCP3 IFCP2 IFCP1
REFERENCE
CHARGE
PUMP
RSET
12-BIT IF
B-COUNTER
FEATURES
ADF4210: 550 MHz/1.2 GHz
ADF4211: 550 MHz/2.0 GHz
ADF4212: 1.0 GHz/2.7 GHz
ADF4213: 1.0 GHz/3 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler
RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Analog and Digital Lock Detect
Fastlock Mode
Power-Down Mode
APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency
synthesizer that can be used to implement local oscillators (LO)
in the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro-
grammable reference divider, programmable A and B Counters
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(12-bit) counters, in conjunction with the dual modulus prescaler
(P/P + 1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase-
Locked Loop) can be implemented if the synthesizer is used with
an external loop filter and VCO (Voltage Controlled Oscillators).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5 V and can be powered down when not in use.


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