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AD9248BST-20 数据表(PDF) 1 Page - Analog Devices |
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AD9248BST-20 数据表(HTML) 1 Page - Analog Devices |
1 / 23 page 14-Bit, 20/40/65 MSPS Dual A/D Converter Preliminary Technical Data AD9248 Rev. PrE 6/29/2004 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703© 2004 Analog Devices, Inc. All rights reserved. FEATURES Integrated Dual 14-Bit A-to-D Converters Single 3 V Supply Operation (2.7 V to 3.6 V) SNR = 73 dBc (to Nyquist, AD9248-65) SFDR = 83 dBc (to Nyquist, AD9248-65) Low Power: 600 mW at 65 MSPS Differential Input with 500 MHz 3 dB Bandwidth Exceptional Cross Talk Immunity > 85dB Flexible Analog Input: 1 V p-p to 2 V p-p Range Offset Binary or Twos Complement Data Format Clock Duty Cycle Stabilizer APPLICATIONS Ultrasound Equipment IF Sampling in Communications Receivers: IS-95, CDMA One, IMT-2000 Battery-Powered Instruments Hand-Held Scopemeters Low Cost Digital Oscilloscopes GENERAL DESCRIPTION The AD9248 is a dual, 3 V, 14-bit, 20/40/65 MSPS analog-to- digital converter. It features dual high performance sample-and hold amplifiers and an integrated voltage reference. The AD9248 uses a multistage differential pipelined architecture with output error correction logic to provide 14-bit accuracy and guarantee no missing codes over the full operating temperature range at up to 65 MSPS data rates. The wide bandwidth, differential SHA allows for a variety of user selectable input ranges and offsets including single-ended applications. It is suitable for various applications including multiplexed systems that switch full-scale voltage levels in successive channels and for sampling inputs at frequencies well beyond the Nyquist rate. Dual single-ended clock inputs are used to control all internal conversion cycles. A duty cycle stabilizer is available on the AD9248-65 and can compensate for wide variations in the clock duty cycle, allowing the converters to maintain excellent performance. The digital output data is presented in either straight binary or twos complement format. Out-of-range signals indicate an overflow condition, which can be used with the most significant bit to determine low or high overflow. Fabricated on an advanced CMOS process, the AD9248 is available in a space saving 64-lead LQFP and is specified over the industrial temperature range (–40? C to +85? C). ADC D13 A-D0A AGND VIN- _A CLK_A AD9248 SHA 14 VIN+_A DCS SENSE REFT_A 14 AVDD ADC VIN-_B SHA VIN+_B 14 D13 B-D0B 14 MUX_SELECT CLK_B AGND DRGND SHARED_REF PWDN_A DFS Mode Control + - REFB_A REFT_B REFB_B Clock Duty Cycle Stabilizer PWDN_B OTR_B OEB_B OEB_A OTR_A 0.5V VREF DRVDD Figure 1. Functional Block Diagram PRODUCT HIGHLIGHTS 1. Pin compatible with AD9238, 12-bit 20/40/65MSPS ADC. 2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS allow flexibility between power, cost, and performance to suit an application. 3. Low power consumption: AD9248-65: 65 MSPS = 600 mW. AD9248-40: 40 MSPS = 330 mW. AD9248-20: 20 MSPS = 180 mW. 4. The patented SHA input maintains excellent performance for input frequencies up to 100 MHz and can be configured for single-ended or differential operation. 5. Typical channel isolation of 85 dB @ fIN = 10 MHz. 6. The clock duty cycle stabilizer (AD9248-65 only) maintains performance over a wide range of clock duty cycles. 7. The OTR output bits indicate when either input signal is beyond the selected input range. 8. Multiplexed data output option enables single-port operation from either data port A or data port B. |
类似零件编号 - AD9248BST-20 |
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类似说明 - AD9248BST-20 |
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