TS68EN360VR25L datasheet(6/82 Pages) ATMEL

部件名	TS68EN360VR25L

功能描述	32-bitQuad Integrated Communication Controller

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制造商	ATMEL [ATMEL Corporation]

网页	http://www.atmel.com

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TS68EN360

2113A–HIREL–03/02

Signal Index

Table 1. System Bus Signal Index (Normal Operation)

Group

Signal Name

Mnemonic

Function

Address

Address Bus

A27-A0

Lower 27 bits of address bus. (I/O)

Address Bus/Byte Write

Enables

A31-A28

WE3-WE0

Upper four bits of address bus (I/O), or byte write enable

signals (O) for accesses to external memory or peripherals.

Function Codes

FC3-FC0

Identifies the processor state and the address space of the

current bus cycle. (I/O)

Data

Data Bus 31 - 16

D31-D16

Upper 16-bit data bus used to transfer byte or word data.

Used in 16-bit bus mode. (I/O)

Data Bus 15 - 0

D15-D0

Lower 16-bit data bus used to transfer 3-byte or long-word

data. (I/O)

Not used in 16-bit bus mode.

Parity

Parity 2 - 0

PRTY2-PRTY0

Parity signals for byte writes/reads from/to external memory

module. (I/O)

Parity 3/16BM

PRTY3/16BM

Parity signals for byte writes/reads from/to external memory

module or defines 16-bit bus mode. (I/O)

Parity Error

PERR

Indicates a parity error during a read cycle. (O)

Memory

Controller

Chip Select

Row Address Select 7

Interrupt Acknowledge 7

CS

RAS7

IACK7

Enables peripherals or DRAMs at programmed addresses

(O) or interrupt level 7 acknowledge line. (O)

Chip Select 6-0

Row Address Select 6-0

CS6-CS0

RAS6-RAS0

Enables peripherals or DRAMs at programmed addresses.

(O)

Column Address Select

3 - 0/Interrupt

Acknowledge 1, 2, 3, 6

CAS3-CAS0/

IACK6,3,2,1

DRAM column address select or interrupt level acknowledge

lines. (O)

Bus Arbitration

Bus Request

BR

Indicates that an external device requires bus mastership. (I)

Bus Grant

BG

Indicates that the current bus cycle is complete and the

QUICC has relinquished the bus. (O)

Bus Grand Acknowledge

BGACK

Indicates that an external device has assumed bus

mastership. (I)

Read-Modify-Write Cycle

Initial Configuration 0

RMC

CONFIG0

Identifies the bus cycle as part of an indivisible

read-modify-write operation (I/O) or initial QUICC

configuration select. (I)

Bus Clear Out/Initial

Configuration 1/Row

Address Select 2

Double-Drive

BCLRO/CONFIG1/

RAS2DD

Indicates that an internal device requires the external bus

(Open-Drain O) or initial QUICC configuration select (I) or

row address select 2 double-drive output. (O)

类似零件编号 - TS68EN360VR25L

制造商	部件名	数据表	功能描述
STMicroelectronics	TS68000	4Mb / 76P	HMOS 16/32-BIT MICROPROCESSOR
	TS68000CFN10	4Mb / 76P	HMOS 16/32-BIT MICROPROCESSOR
	TS68000CFN16	4Mb / 76P	HMOS 16/32-BIT MICROPROCESSOR
	TS68000CFN8	4Mb / 76P	HMOS 16/32-BIT MICROPROCESSOR
	TS68000CP10	4Mb / 76P	HMOS 16/32-BIT MICROPROCESSOR

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