5

TPA3113D2

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SLOS650F – AUGUST 2009 – REVISED JUNE 2016

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Copyright © 2009–2016, Texas Instruments Incorporated

Pin Functions (continued)

PIN

DESCRIPTION

NO.

NAME

19

PGND

—

Power ground for the H-bridges.

20

OUTNR

O

Class-D H-bridge negative output for right channel.

21

BSNR

I

Bootstrap I/O for right channel, negative high-side FET.

22

BSNL

I

Bootstrap I/O for left channel, negative high-side FET.

23

OUTNL

O

Class-D H-bridge negative output for left channel.

24

PGND

—

Power ground for the H-bridges.

25

OUTPL

O

Class-D H-bridge positive output for left channel.

26

BSPL

I

Bootstrap I/O for left channel, positive high-side FET.

27

PVCCL

P

Power supply for left channel H-bridge. Right channel and left channel power

supply inputs are connect internally.

28

PVCCL

P

Power supply for left channel H-bridge. Right channel and left channel power

supply inputs are connect internally.

29

PowerPAD

—

Connect to ground

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

The voltage slew rate of these pins must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resister in series

with the pins.

(3)

The TPA3113D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected

to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection

shutdown. See TI Technical Briefs Quad Flatpack No-Lead Logic Packages for more information about using the TSSOP thermal pad.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

AVCC, PVCC

–0.3

30

V

Interface pin

voltage

–0.3

V

< 10

V/ms

PLIMIT

–0.3

GVDD + 0.3

V

RINN, RINP, LINN, LINP

–0.3

6.3

V

Continuous total power dissipation

See Thermal Information

Operating free-air temperature

–40

85

°C

–40

150

°C

Minimum load

resistance

BTL: PVCC > 15 V

4.8

Ω

BTL: PVCC

≤ 15 V

3.2

PBTL

3.2

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

In accordance with JEDEC Standard 22, Test Method A114-B.

(3)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(4)

In accordance with JEDEC Standard 22, Test Method C101-A

6.2 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±2000

V

Charged-device model (CDM), per JEDEC specification JESD22-

±500