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TPA3111D1 数据表(PDF) 11 Page - Texas Instruments |
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TPA3111D1 数据表(HTML) 11 Page - Texas Instruments |
11 / 31 page + + ± ± + + ± ± + ± + ± PLIMIT PLIMIT Reference Gain Control TTL Buffer LDO Regulator Ramp Generator Biases and References Startup Protection Logic SC Detect DC Detect Thermal Detect UVLO and OVLO Gate Drive Gate Drive PWM Logic AGND GVDD GVDD AVCC AVCC PLIMIT GAIN1 GAIN0 SD FAULT INN INP OUTN FB Gain Control OUTP FB GVDD PVCC PVCC PVCC PVCC GVDD OUTN FB OUTP FB OUTN PGND BSN PGND OUTP BSP Copyright © 2016, Texas Instruments Incorporated 11 TPA3111D1 www.ti.com SLOS618F – AUGUST 2009 – REVISED JULY 2016 Product Folder Links: TPA3111D1 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Gain Setting Through GAIN0 and GAIN1 Inputs The gain of the TPA3111D1 is set by two input pins, GAIN0 and GAIN1. The voltage slew rate of these gain pins, along with SD and AVCC (pin 14), must be restricted to no more than 10 V/ms. For higher slew rates, use a 100-kΩ resistor in series with the pins. The gains listed in Table 1 are realized by changing the taps on the input resistors inside the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance from part to part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors. For design purposes, the input network must be designed assuming an input impedance of 7.2 k Ω, which is the absolute minimum input impedance of the TPA3111D1. At the lower gain settings, the input impedance could increase as high as 72 k Ω Table 1. Gain Setting GAIN1 GAIN0 AMPLIFIER GAIN (dB) INPUT IMPEDANCE (k Ω) TYPICAL TYPICAL 0 0 20 60 0 1 26 30 1 0 32 15 1 1 36 9 |
类似零件编号 - TPA3111D1 |
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类似说明 - TPA3111D1 |
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