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AK5558VN 数据表(PDF) 57 Page - Asahi Kasei Microsystems |
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AK5558VN 数据表(HTML) 57 Page - Asahi Kasei Microsystems |
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57 / 70 page  [AK5558] 015099850-E-00 2016/03 - 57 - [2] DSD mode The Internal PDN is released by inputting MCLK after setting the PDN pin to “H”. PDN pin Power-Down Normal Operation MCLK In ADC In (Analog) DSD Out (Digital) Don ’t care (3) “L” (-full scale data) Don ’t care Internal State (4) (1) (2) Initialize Power-Down OVF-pin normal data abnormal data normal data “L” (-full scale data) (6) (5) Internal PDN Figure 61. DSD Operation Timing Notes: (1) Th e internal LDO is powered up by releasing PDN pin to “H”. The internal PDN is released by toggling internal oscillator clock for 16384 times (max. 10ms). The internal PDN is released in max. 1 ms after releasing PDN pin to “H”. Register writings become available when the internal PDN changes to “1”. During this period, digital output and digital in/output pins may output an instantaneous pulse (max. 1 us). Therefore, referring the output of digital pins and data transmission with a device on the same 3-wire serial/I 2C bus as the AK5558 should be avoided in this period to prevent system errors. (2) Initialization operation will be completed in 583/fs. (3) DSD output pins output “L” (-full scale data) during power down and initializing operation. DSD output pins output full scale data during phase modulation mode, a reset sequence and a CH power down status. (4) The OVF pin outputs “H” when an excessive signal is input and overflow is detected at internal modulator. The OVF pin status will change after group delay period from the excessive input. (5) In the case above (4), the DSD output data will not be correct. (6) The OVF pin returns to “L” when the input signal settled to a normal state and overflow status of the internal modulator is resolved. The OVF pin status will change after group delay period from the normal input. |
类似零件编号 - AK5558VN_16 |
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类似说明 - AK5558VN_16 |
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