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STK6005F 数据表(PDF) 11 Page - List of Unclassifed Manufacturers |
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STK6005F 数据表(HTML) 11 Page - List of Unclassifed Manufacturers |
11 / 36 page 11 STK6005 5.2 Output Timing and Format The output interface consists of two pixel ports, each containing Red / Green / Blue in colors with 6 or 8 bits of resolution. There are three output control signals for panel – PVS, PHS and PDE. The output pixels and control signals above are all synchronous to the active edge of panel output clock DCLK. The polarity of output clock / control signals and the timing of the active edge of output clock are programmable by setting the internal registers. There are two output formats – single / dual pixels output modes. In single pixel output mode, pixel data are output from PE_R/G/B ports only, and the PO_R/G/B ports are disabled. In dual pixel output mode, pixel data are output to both PE_R/G/B and PO_R/G/B ports in parallel. The first pixel of a line will be output to PE_R/G/B ports and the second pixel will be output to PO_R/G/B ports. Back to Contents Table VCLK Cref Y(RIN) Y0 Y1 Y2 UV(GIN) U0 V0 U2 Hsync/Vsync /Field Href/Vref YUV16 input format timing diagram |
类似零件编号 - STK6005F |
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类似说明 - STK6005F |
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