4-Channel DAS with 16-Bit, Bipolar Input,

Simultaneous Sampling ADC

Data Sheet

AD7605-4

Rev. 0

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FEATURES

4 simultaneously sampled inputs

True bipolar analog input ranges: ±10 V (maximum),

±5 V (maximum)

Fully integrated data acquisition solution

Analog input clamp protection

Input buffer with 1 MΩ analog input impedance

Second-order antialiasing analog filter

On-chip accurate reference and reference buffer

16-bit ADC with 300 kSPS on all channels

Flexible parallel/serial interface

Serial peripheral interface (SPI)/QSPI/MICROWIRE/DSP

compatible

Performance

7 kV ESD rating on analog input pins

Standby mode: 25 mW (typical)

64-lead LQFP package

APPLICATIONS

Power line monitoring and protection systems

Multiphase motor control

Instrumentation and control systems

Multiaxis positioning systems

Data acquisition systems (DAS)

GENERAL DESCRIPTION

The AD7605-41 is a 4-channel, 16-bit, simultaneous sampling,

analog-to-digital data acquisition system (DAS). The device

contains analog input clamp protection, a second-order antialias-

ing filter, a track-and-hold amplifier, a 16-bit charge redistribution

successive approximation analog-to-digital converter (ADC), a

2.5 V reference and reference buffer, and high speed serial and

parallel interfaces.

The AD7605-4 operates from a single 5 V supply and can

accommodate ±10 V and ±5 V true bipolar input signals while

sampling at throughput rates of up to 300 kSPS for all channels.

The input clamp protection circuitry can tolerate voltages up to

±16.5 V. The AD7605-4 has 1 MΩ analog input impedance,

regardless of sampling frequency. The single-supply operation,

on-chip filtering, and high input impedance eliminate the need

for driver op amps and external bipolar supplies.

The AD7605-4 is SPI, QSPI™, MICROWIRE™, and digital signal

processor (DSP) compatible.

Table 1. High Resolution, Bipolar Input, Simultaneous

Sampling DAS Solutions

Resolution

(Bits)

Single-Ended

Inputs

True Differential

Inputs

No. of Simultaneous

Sampling Channels

18

AD7608

AD7609

8

16

AD7606

8

AD7606-6

6

AD7606-4

4

AD7605-4

4

14

AD7607

8

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

1

Protected by U.S. Patent No. 8,072,360 B2.

V1

V1GND

1MΩ

1MΩ

CLAMP

CLAMP

SECOND-

ORDER LPF

T/H

V2

V2GND

1MΩ

1MΩ

CLAMP

CLAMP

SECOND-

ORDER LPF

T/H

V3

V3GND

1MΩ

1MΩ

CLAMP

CLAMP

SECOND-

ORDER LPF

T/H

V4

V4GND

1MΩ

1MΩ

CLAMP

CLAMP

SECOND-

ORDER LPF

T/H

4:1

MUX

AGND

BUSY

FRSTDATA

CONVST A CONVST B RESET RANGE

CONTROL

INPUTS

CLK OSC

REFIN/REFOUT

REF SELECT

AGND

RD/SCLK

CS

PAR/SER/BYTE SEL

16-BIT

SAR

PARALLEL/

SERIAL

INTERFACE

2.5V

REF

REFCAPB REFCAPA

SERIAL

PARALLEL

REGCAP

2.5V

LDO

REGCAP

2.5V

LDO

DB0 TO DB15/BYTESEL

AD7605-4