CDC208

DUAL 1-LINE TO 4-LINE CLOCK DRIVER

WITH 3-STATE OUTPUTS

SCAS109F – APRIL 1990 – REVISED OCTOBER 1998

1

POST OFFICE BOX 655303

Specifications for Clock-Driver

Applications

CMOS-Compatible Outputs

PCB Layout

Configurations Minimize High-Speed

Switching Noise

CMOS) 1-

µm Process

125

°C

Small-Outline (DW)

description

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew

for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each

circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level

independent of the signal on the respective A input.

Skew parameters are specified for a reduced temperature and voltage range common to many applications.

The CDC208 is characterized for operation from – 40

°C to 85°C.

FUNCTION TABLES

INPUTS

OUTPUTS

1OE1

1OE2

1A

1Y1

1Y2

1Y3

1Y4

L

L

L

L

L

L

L

L

LH

H

HH

H

L

HX

L

LL

L

H

LX

H

HH

H

H

H

X

Z

Z

Z

Z

INPUTS

OUTPUTS

2OE1

2OE2

2A

2Y1

2Y2

2Y3

2Y4

L

L

L

L

L

L

L

L

LH

H

HH

H

L

HX

L

LL

L

H

LX

H

HH

H

H

H

X

Z

Z

Z

Z

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1Y2

1Y3

1Y4

GND

GND

GND

GND

2Y1

2Y2

2Y3

1Y1

1A

1OE1

1OE2

2A

2OE1

2OE2

2Y4

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