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STK17TA8-W35I 数据表(PDF) 10 Page - List of Unclassifed Manufacturers |
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STK17TA8-W35I 数据表(HTML) 10 Page - List of Unclassifed Manufacturers |
10 / 22 page STK17TA8 February 2004 10 Document Control # ML0023 rev 0.3 nvSRAM The STK17TA8 has two separate modes of opera- tion: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to the nonvolatile elements (the STORE operation) or from the nonvolatile elements to SRAM (the RECALL operation). In this mode SRAM func- tions are disabled. The STK17TA8 supports unlim- ited reads and writes to the SRAM, unlimited recalls from the nonvolatile elements and up to 1 million stores to the nonvolatile elements SRAM READ The STK17TA8 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A 0-16 determines which of the 131,072 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of t AVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at t ELQV or at t GLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the t AVQV access time without the need for tran- sitions on any control input pins, and will remain valid until another address change or until E or G is brought high, or W is brought low. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ 0-7 will be writ- ten into the memory if it is valid t DVWH before the end of a W controlled WRITE or t DVEH before the end of an E controlled WRITE. It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers t WLQZ after W goes low. AutoStore™ OPERATION The STK17TA8 can be powered in one of three modes. During normal operation, the STK17TA8 will draw current from V CCX to charge a capacitor connected to the V CAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the V CCX pin drops below V SWITCH, the part will automatically disconnect the V CAP pin from VCCX and initiate a STORE opera- tion. Figure 2 shows the proper connection of capacitors for automatic store operation. A charge storage capacitor having a capacity of between 10 µF and 100 µF (± 20%) rated at minimum of 5V should be provided. In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB low, will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initi- ated STORE cycles are performed regardless of whether a WRITE operation has taken place. HSB can be used to signal the system that the AutoStore™ cycle is in progress. HSB OPERATION The STK17TA8 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK17TA8 will conditionally initiate a STORE operation after t DELAY; an actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or Figure 2: AutoStore™ Mode If HSB is not used it should be left uncon nected Vcap Vss Vccx + 10k Ω∗ W DEVICE OPERATION |
类似零件编号 - STK17TA8-W35I |
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类似说明 - STK17TA8-W35I |
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