FAN4810

PRODUCT SPECIFICATION

10

REV. 1.0.12 9/24/03

Oscillator (RAMP 1)

The oscillator frequency is determined by the values of RT

oscillator output clock:

The dead time of the oscillator is derived from the following

equation:

The dead time of the oscillator may be determined using:

operating frequency can typically be approximated by:

EXAMPLE:

For the application circuit shown in the data sheet, with the

oscillator running at:

Clock Out (Pin 11)

Clock output is a rail to rail CMOS driver. The PMOS can

pull up within 15 ohms of the rail and the NMOS can pull

down to within 7 ohms of ground.

The clock turns on when the CLKSD pin is greater than

1.25V and the PFC output voltage is at rated operation value.

The clock signal can be used to synchronize and provide on/

off control for downstream DC to DC PWM converters.

CLKSD (Pin 5)

A current source of 25µA supplies the charging current for a

capacitor connected to this pin. Start-up delay can be pro-

grammed by the following equation:

is the desired start-up delay.

It is important that the start-up delay is long enough to allow

the PFC time to generate sufficient output power for the

PWM DC converter. The start-up delay should be at least

5ms.

The FAN4810 is a voltage-fed part. It requires an external

15V, ±10% (or better) shunt voltage regulator, or some other

15V nominal. This allows low power dissipation while at the

same time delivering 13V nominal gate drive at the PFC

OUT output. If using a Zener diode for this function, it is

important to limit the current through the Zener to avoid

overheating or destroying it. This can be easily done with a

single resistor in series with the Vcc pin, returned to a bias

supply of typically 18V to 20V. The resistor’s value must be

chosen to meet the operating current requirement of the

FAN4810 itself (7mA, max.) plus the current required by the

gate driver output and zener diode.

EXAMPLE:

driving a total gate charge of 38nC at 100kHz (e.g., 1

IRF840 MOSFET ), the gate driver current required is:

The FAN4810 should be locally bypassed with a 1.0µF

ceramic capacitor. In most applications, an electrolytic

capacitor of between 47µF and 220µF is also required across

the part, both for filtering and as part of the start-up bootstrap

circuitry.

Typical Applications

Figure 4 is the application circuit for a complete 125W

power factor corrected power supply, designed using the

methods and general topology detailed in Application Note

42046.

f

OSC

1

t

RAMP

t

DEADTIME

+

----------------------------------------------------

=

(2)

t

RAMP

C

T

R

T

×

In

V

REF

1.25

–

V

REF

3.75

–

------------------------------

×

=

(3)

t

RAMP

C

T

R

T

×

0.51

×

=

t

DEADTIME

2.5V

5.5mA

-----------------

C

T

×

450

C

T

×

==

(4)

f

OSC

1

t

RAMP

----------------

=

(5)

f

OSC

100kHz

1

t

RAMP

----------------

==

C

dly

t

DELAY

25

µA

1.25V

---------------

×

=

(6)

C

dly

5ms

25

µA

1.25V

---------------

×

100nF

==

(6a)

I

GATEDRIVE

100kHz

38nC

×

3.8mA

==

(7)

R

BIAS

V

BIAS

V

CC

–

I

CC

I

G

I

Z

++

---------------------------------

=

(8)

R

BIAS

20V

15V

–

7mA

3.8mA

5mA

++

-------------------------------------------------------

316

Ω

==