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CS7410 数据表(PDF) 11 Page - Cirrus Logic |
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CS7410 数据表(HTML) 11 Page - Cirrus Logic |
11 / 39 page CS7410 DS553PP1 11 1.1.4.2 Serial Interface Symbol Description Min Typ Max Unit tclk_per Clock period 66 ns tDMs Master-mode data setup 28 ns tDMh Master-mode data hold 28 ns tDSs Slave-mode data setup 15 ns tCMs Master chip select to clock setup 28 ns tDSh Slave mode data hold 0 ns Table 2. Serial Interface Characterization Data SER2_CLK (CPOL=0) SER2_CLK (CPOL=1) SER2_DO (master) SER2_DI (slave) SER2_CS MSB LSB LSB MSB t clk_per t DMs t DMh t DSs t DSh t CMs Figure 6. Serial Interface Timing Diagram |
类似零件编号 - CS7410 |
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类似说明 - CS7410 |
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