ADF5901 datasheet(5/27 Pages) AD

部件名	ADF5901

功能描述	24 GHz to 24.25 GHz voltage controlled oscillator

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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5 / 27 page

ADF5901

Data Sheet

Rev. A | Page 4 of 26

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ADC

Resolution

8

Bits

Integral Nonlinearity (INL)

±1

LSB

Differential Nonlinearity (DNL)

±1

LSB

Least Significant Bit (LSB)

7.4

mV

REFIN CHARACTERISITICS

REFIN Input Frequency

10

260

MHz

−5 dBm minimum to +9 dBm maximum biased

at AHI/2 (ac coupling ensures 1.8/2 bias); for

frequencies < 10 MHz, use a dc-coupled, CMOS-

compatible square wave with a slew rate >

25 V/µs

REFIN Input Capacitance

1.2

pF

REFIN Input Current

±100

µA

LOGIC INPUTS

Input Voltage

High (VIH)

1.4

V

Low (VIL)

0.6

V

Input Current (IINH, IINL)

±1

µA

Input Capacitance (CIN)

10

pF

LOGIC OUTPUTS

Output Voltage

High (VOH)2

VDD −

0.4

V

Low (VOL)

0.4

V

Output Current

High (IOH)

500

µA

Low (IOL)

500

µA

1

TA = 25°C; AHI = 3.3 V; fREFIN = 100 MHz; RF = 24.125 GHz following initialization sequence in the Initialization Sequence section.

2

VDD selected from IO level bit (DB11 in Register 3).

TIMING SPECIFICATIONS

AHI = TX_AHI = RF_AHI = VCO_AHI = DVDD = 3.3 V ± 5%, AGND = 0 V, dBm referred to 50 Ω, TA = TMIN to TMAX, unless otherwise

noted. Operating temperature range is −40°C to +105°C.

Table 2. Write Timing

Parameter

Limit at TMIN to TMAX

Unit

Description

t1

20

ns min

LE setup time

t2

10

ns min

DATA to CLK setup time

t3

10

ns min

DATA to CLK hold time

t4

25

ns min

CLK high duration

t5

25

ns min

CLK low duration

t6

10

ns min

CLK to LE setup time

t7

20

ns min

LE pulse width

t8

10

ns max

LE setup time to DOUT

t9

15

ns max

CLK setup time to DOUT

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