数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

STK10C48-P25I 数据表(PDF) 7 Page - List of Unclassifed Manufacturers

部件名 STK10C48-P25I
功能描述  2K X 8 NVSRAM
Download  9 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  ETC [List of Unclassifed Manufacturers]
网页  
标志 ETC - List of Unclassifed Manufacturers

STK10C48-P25I 数据表(HTML) 7 Page - List of Unclassifed Manufacturers

  STK10C48-P25I Datasheet HTML 1Page - List of Unclassifed Manufacturers STK10C48-P25I Datasheet HTML 2Page - List of Unclassifed Manufacturers STK10C48-P25I Datasheet HTML 3Page - List of Unclassifed Manufacturers STK10C48-P25I Datasheet HTML 4Page - List of Unclassifed Manufacturers STK10C48-P25I Datasheet HTML 5Page - List of Unclassifed Manufacturers STK10C48-P25I Datasheet HTML 6Page - List of Unclassifed Manufacturers STK10C48-P25I Datasheet HTML 7Page - List of Unclassifed Manufacturers STK10C48-P25I Datasheet HTML 8Page - List of Unclassifed Manufacturers STK10C48-P25I Datasheet HTML 9Page - List of Unclassifed Manufacturers  
Zoom Inzoom in Zoom Outzoom out
 7 / 9 page
background image
STK10C48
July 1999
3-7
The STK10C48 has two modes of operation: SRAM
mode and nonvolatile mode, determined by the
state of the NE pin. When in SRAM mode, the mem-
ory operates as a standard fast static RAM. While in
nonvolatile mode, data is transferred in parallel from
SRAM
to EEPROM or from EEPROM to SRAM.
NOISE CONSIDERATIONS
Note that the STK10C48 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1
µF connected between V
CC
and V
SS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK10C48 performs a READ cycle whenever E
and G are low and NE and W are high. The address
specified on pins A
0-10 determines which of the 2,048
data bytes will be accessed. When the READ is initi-
ated by an address transition, the outputs will be
valid after a delay of t
AVQV (READ cycle #1). If the
READ
is initiated by E or G, the outputs will be valid
at t
ELQV or at tGLQV, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address
changes within the t
AVQV access time without the need
for transitions on any control input pins, and will
remain valid until another address change or until E
or G is brought high or W or NE is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and NE is high. The address inputs must be sta-
ble prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on pins DQ
0-7 will be writ-
ten into the memory if it is valid t
DVWH before the end
of a W controlled WRITE or t
DVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
WLQZ after W goes low.
NONVOLATILE STORE
A STORE cycle is performed when NE, E and W and
low and G is high. While any sequence that
achieves this state will initiate a STORE, only W initi-
ation (STORE cycle #1) and E initiation (STORE cycle
#2) are practical without risking an unintentional
SRAM WRITE
that would disturb SRAM data. During a
STORE
cycle, previous nonvolatile data is erased
and the SRAM contents are then programmed into
nonvolatile elements. Once a STORE cycle is initi-
ated, further input and output are disabled and the
DQ
0-7 pins are tri-stated until the cycle is complete.
If E and G are low and W and NE are high at the end
of the cycle, a READ will be performed and the out-
puts will go active, signaling the end of the STORE.
NONVOLATILE RECALL
A RECALL cycle is performed when E, G and NE are
low and W is high. Like the STORE cycle, RECALL is
initiated when the last of the four clock signals goes
to the RECALL state. Once initiated, the RECALL
cycle will take t
NLQX to complete, during which all
inputs are ignored. When the RECALL completes,
any READ or WRITE state on the input pins will take
effect.
Internally, RECALL is a two-step procedure. First, the
SRAM
data is cleared, and second, the nonvolatile
information is transferred into the SRAM cells. The
RECALL
operation in no way alters the data in the
nonvolatile cells. The nonvolatile data can be
recalled an unlimited number of times.
As with the STORE cycle, a transition must occur on
any one control pin to cause a RECALL, preventing
inadvertent multi-triggering. On power up, once V
CC
exceeds 4.25V, a RECALL cycle is automatically ini-
tiated. Due to this automatic RECALL, SRAM opera-
tion cannot commence until t
RESTORE
after V
CC
exceeds 4.25V.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CC
< 3.0V), an internal RECALL request will be
latched. When V
CC once again exceeds 4.25V, a
RECALL
cycle will automatically be initiated and will
take t
RESTORE to complete.
DEVICE OPERATION


类似零件编号 - STK10C48-P25I

制造商部件名数据表功能描述
logo
Simtek Corporation
STK10C48-P25I SIMTEK-STK10C48-P25I Datasheet
429Kb / 12P
   2K x 8 nvSRAM QuantumTrap??CMOS Nonvolatile Static RAM
More results

类似说明 - STK10C48-P25I

制造商部件名数据表功能描述
logo
Simtek Corporation
U631H16 SIMTEK-U631H16 Datasheet
133Kb / 13P
   SimtekSoftStore 2K x 8 nvSRAM
U630H16 SIMTEK-U630H16 Datasheet
152Kb / 15P
   HardStore 2K x 8 nvSRAM
logo
List of Unclassifed Man...
U63716 ETC-U63716 Datasheet
206Kb / 13P
   CAPSTORE 2K X 8 NVSRAM
STK25C48 ETC-STK25C48 Datasheet
84Kb / 8P
   2K X 8 AUTOSTORE NVSRAM
U631H16 ETC-U631H16 Datasheet
275Kb / 12P
   SOFTSTORE 2K X 8 NVSRAM
logo
Simtek Corporation
U635H16 SIMTEK-U635H16 Datasheet
137Kb / 14P
   PowerStore 2K x 8 nvSRAM
U630H16P SIMTEK-U630H16P Datasheet
178Kb / 17P
   HardStore 2K x 8 nvSRAM
U632H16 SIMTEK-U632H16 Datasheet
403Kb / 15P
   PowerStore 2K x 8 nvSRAM
U630H16PA35 SIMTEK-U630H16PA35 Datasheet
324Kb / 15P
   HardStore 2K x 8 nvSRAM
logo
List of Unclassifed Man...
U630H16 ETC-U630H16 Datasheet
212Kb / 14P
   HARDSTORE 2K X 8 NVSRAM
More results


Html Pages

1 2 3 4 5 6 7 8 9


数据表 下载

Go To PDF Page


链接网址




隐私政策
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com