ISL29034

10

FN8370.2

August 19, 2016

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Command-II Register (Address: 0x01)

The Command-II register consists of ADC control bits. In this

register, there are two range bits and two ADC resolution bits.

The default register value is 0x00 at power-on.

FULL SCALE LUX RANGE [B1:B0]

The full scale Lux range has four different selectable ranges. The

range determines the full scale Lux range (1k, 4k, 16k, and 64k).

Each range has a maximum allowable Lux value. Table 7 lists the

possible values of FSR.

Integration Time ADC Resolution [B3:B2]

B2 and B3 determine the ADC’s resolution and the number of

clock cycles per conversion. Changing the number of clock cycles

does more than just change the resolution of the device; it also

changes the integration time, which is the period the device’s

Analog-to-Digital (A/D) converter samples the photodiode current

signal for a measurement. Table 8 lists the possible ADC

resolution. Only 16 bit ADC resolution can reject better

50Hz/60Hz noise flickering light source.

.

Integration Time

Data Registers (Addresses: 0x02 and 0x03)

The ISL29034 has two 8-bit read-only registers to hold the upper

and lower byte of the ADC value. The Upper byte is accessed at

Address 0x03 and the Lower byte is accessed at Address 0x02.

For 16-bit resolution, the data is from D0 to D15; for 12-bit

resolution, the data is from D0 to D11; for 8-bit resolution, the

data is from D0 to D7 and for 4-bit resolution, the data is from

D0 to D3. The registers are refreshed after every conversion

cycle. The default register value is 0x00 at power-on.

ID Register (Address: 0x0F)

The ID register has three different types of information.

TABLE 5. OPERATING MODES BITS

B7

B6

B5

OPERATION

0

0

0

Power-down the device (Default)

0

0

1

The device measures ALS only once every integration

cycle. This is the lowest operating mode. (Note 11)

01

0

IR once

0

1

1

Reserved (Do Not Use)

1

0

0

Reserved (Do Not Use)

1

0

1

Measures ALS continuously

1

1

0

Measures IR continuous

1

1

1

Reserved (Do Not Use)

NOTE:

11. Intersil does not recommend using this mode

TABLE 6. COMMAND-II REGISTER BITS

NAME

REG.

ADDR

(HEX)

REGISTER BITS

DFLT

(HEX)

B7 B6 B5 B4 B3

B2

B1

B0

COMMAND

-II

0x01

RESERVED

RES

1

RES

0

RANGE

1

RANGE

0

0x00

TABLE 7. RANGE REGISTER BITS

RANGE

SELECTION

B1

B0

FULL SCALE LUX RANGE

(LUX)

0

0

0

1,000

1

0

1

4,000

2

1

0

16,000

3

1

1

64,000

TABLE 8. ADC RESOLUTION DATA WIDTH

B3

B2

NUMBER OF CLOCK CYCLES

n-BIT ADC

00

16

01

12

10

8

11

4

TABLE 9. INTEGRATION TIME OF n-BIT ADC

n # ADC BITS

INTEGRATION TIME (ms)

4

0.022

8

0.352

12

5.6

16

105

TABLE 10. ADC REGISTER BITS

NAME

Reg.

Addr

(HEX)

REGISTER BITS

DFLT

(HEX)

B7

B6

B5

B4

B3

B2

B1

B0

D6

D5

D4

D3

D2

D1

D0 0x00

D8 0x00

TABLE 11. ADC DATA REGISTERS

ADDRESS

(HEX)

CONTENTS

0x02

D0 is LSB for 4-, 8-, 12- or 16-bit resolution; D3 is MSB for

4-bit resolution; D7 is MSB for 8-bit resolution

0x03

D15 is MSB for 16-bit resolution; D11 is MSB for 12-bit

resolution

TABLE 12. ID REGISTER BITS

NAME

ADDR

(HEX)

REGISTER BITS

DFLT

B7

B6

B5 B4 B3 B2 B1 B0

ID

0x0F BOUT RESERVED 1

0

1 RESERVED 1x101xxx