2.3 Input Bias Resistors

Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The non-inverting

CLK0 or

CLK1

+

–

Figure 2.5. Input Bias Resistors

Note: To minimize the possibility of system noise coupling into the Si5334x differential inputs and adversely affecting the buffered out-

put, Silicon Labs recommends 1 PPS clocks and disabled/gapped clocks be DC-coupled and driven “stop-low” .

2.4 Input Mux

The Si5334x provide two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects

the active clock input. The following table summarizes the input and output clock based on the input mux and output enable pin set-

tings.

Table 2.3. Input Mux Logic

CLK_SEL

CLK0

CLK1

Q1

Qb

L

L

X

L

H

L

H

X

H

L

H

X

L

L

H

H

X

H

H

L

Note:

1. On the next negative transition of CLK0 or CLK1.

Si53340-45 Data Sheet

Functional Description

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