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Si53119-A03AGM 数据表(PDF) 1 Page - Silicon Laboratories

部件名 Si53119-A03AGM
功能描述  PLL or bypass mode
Download  34 Pages
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制造商  SILABS [Silicon Laboratories]
网页  http://www.silabs.com
标志 SILABS - Silicon Laboratories

Si53119-A03AGM 数据表(HTML) 1 Page - Silicon Laboratories

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Rev. 1.0 12/15
Copyright © 2015 by Silicon Laboratories
Si53119-A03A
Si53119-A03A
19-O UTPUT PCIE GEN 3 BUFFER
Features
Applications
Description
The Si53119-A03A is a 19-output, low-power HCSL differential clock
buffer that meets all of the performance requirements of the Intel
DB1200ZL specification. To reduce board space and bill of material cost,
the device fully integrates all external resistors, supporting 85
transmission lines. It is optimized for distributing reference clocks for
Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/
Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output can be enabled through I2C
for maximum flexibility and power savings. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it
for free at www.silabs.com/pcie-learningcenter.
Nineteen 0.7 V low-power, push-
pull HCSL PCIe Gen 3 outputs
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
PLL bandwidth SW SMBUS
programming overrides the latch
value from HW pin
9 selectable SMBUS addresses
SMBus address configurable to
allow multiple buffers in a single
control network 3.3 V supply
voltage operation
Separate VDDIO for outputs
Integrated termination resistors
supporting 85
 transmission lines
PLL or bypass mode
Spread spectrum tolerable
1.05 to 3.3 V I/O supply voltage
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
Low phase jitter (Intel® QPI, PCIe
Gen 1/Gen 2/Gen 3/Gen 4
common clock compliant)
100 ps input-to-output delay
Gen3 SRNS Compliant
Extended Temperature:
–40 to 85 °C
72-pin QFN
For variations of this device,
contact Silicon Labs
Server
Storage
Data center
Enterprise switches and routers
Patents pending
Ordering Information:
See page 31.
Pin Assignments
Si53119
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
VDDA
GNDA
100M_133M
HBW_BYPASS_LBW
PWRGD / PWRDN
GND
VDDR
CLK_IN
CLK_IN
SA_0
SDA
SCL
SA_1
FBOUT_NC
GND
DIF_7
DIF_7
GND
VDD
48
47
46
45
44
43
42
41
40
39
38
37
DIF_11
DIF_11
DIF_10
DIF_10
DIF_9
DIF_9
DIF_8
DIF_8
VDD_IO
54
53
52
51
50
49
18
17
DIF_0
DIF_0
VDD_IO
GND
DIF_12
DIF_12
GND
FBOUT_NC


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