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CDCE813QPWRQ1 数据表(PDF) 4 Page - Texas Instruments

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部件名 CDCE813QPWRQ1
功能描述  Programmable 1-PLL Clock Synthesizer and Jitter Cleaner With 2.5-V and 3.3-V Outputs
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

CDCE813QPWRQ1 数据表(HTML) 4 Page - Texas Instruments

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CDCE813-Q1
SNAS705 – JANUARY 2017
www.ti.com
Product Folder Links: CDCE813-Q1
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3)
SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions table.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
VDD
Supply voltage
–0.5
2.5
V
VDDOUT
Output clocks supply voltage
CDCE813-Q1
–0.5
3.6 + 0.5
V
VI
Input voltage(2)(3)
–0.5
VDD + 0.5
V
VO
Output voltage(2)
–0.5
VDDOUT + 0.5
V
II
Input current (VI < 0, VI > VDD)
20
mA
IO
Continuous output current
50
mA
TJ
Maximum junction temperature
125
°C
Tstg
Storage temperature
–65
150
(1)
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002(1)
±2000
V
Charged-device model (CDM), per AEC Q100-011
±1500
7.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VDD
Device supply voltage
1.7
1.8
1.9
V
VO
Output Yx supply voltage, VDDOUT
CDCE813-Q1
2.3
3.6
V
VIL
Low-level input voltage, LVCMOS
0.3 × VDD
V
VIH
High-level input voltage, LVCMOS
0.7 × VDD
V
VI(thresh)
Input voltage threshold, LVCMOS
0.5 × VDD
V
VI(S)
Input voltage range, S0
0
1.9
V
Input voltage range S1, S2, SDA, SCL (VI(thresh) = 0.5 VDD)
0
3.6
VI(CLK)
Input voltage range CLK
0
1.9
V
IOH, IOL
Output current
VDDOUT = 3.3 V
±12
mA
VDDOUT = 2.5 V
±10
CL
Output load, LVCMOS
15
pF
TA
Operating ambient temperature
–40
105
°C


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