MC54/74HC390A

MOTOROLA

High–Speed CMOS Logic Data

DL129 — Rev 6

4

Unit

Guaranteed Limit

VCC

V

Parameter

Symbol

Unit

v 125_C

v 85_C

– 55 to

25

_C

VCC

V

Parameter

Symbol

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

3.0

4.5

6.0

75

27

15

13

95

32

19

15

110

36

22

19

ns

Cin

Maximum Input Capacitance

—

10

10

10

pF

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Counter)*

Typical @ 25

°C, VCC = 5.0 V

pF

CPD

Power Dissipation Capacitance (Per Counter)*

35

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

Symbol

Parameter

VCC

V

Guaranteed Limit

Unit

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

trec

Minimum Recovery Time, Reset Inactive to Clock A or Clock B

(Figure 2)

2.0

3.0

4.5

6.0

25

15

5

5

30

20

6

5

40

30

10

7

ns

tw

Minimum Pulse Width, Clock A, Clock B

(Figure 1)

2.0

3.0

4.5

6.0

75

27

15

13

95

32

19

15

110

36

22

19

ns

tw

Minimum Pulse Width, Reset

(Figure 2)

2.0

3.0

4.5

6.0

75

27

15

13

95

32

19

15

110

36

22

19

ns

tf, tf

Maximum Input Rise and Fall Times

(Figure 1)

2.0

3.0

4.5

6.0

1000

800

500

400

1000

800

500

400

1000

800

500

400

ns

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).