BD3491FS_14 datasheet(7/34 Pages) ROHM

部件名	BD3491FS

功能描述	Sound Processor with Built-in Surround Sound Function

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制造商	ROHM [Rohm]

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Datasheet

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TSZ02201-0C2C0E155560-1-2

1.APR.2014 Rev.004

www.rohm.com

TSZ22111

・15・001

BD3491FS

CONTROL SIGNAL SPECIFICATION

(1) Electrical specifications and timing for bus lines and I/O stages

Figure 12. Definition of timing on the I

2C-BUS

Table 1. Characteristics of the SDA and SCL bus lines for I

2C-BUS devices

Parameter

Symbol

Fast-mode

Unit

Min.

Max.

1

SCL clock frequency

fSCL

0

400

kHz

2

Bus free time between a STOP and START condition

tBUF

1.3

－

µs

3

Hold time (repeated) START condition. After this period, the first clock

pulse is generated

tHD;STA

0.6

－

µs

4

LOW period of the SCL clock

tLOW

1.3

－

µs

5

HIGH period of the SCL clock

tHIGH

0.6

－

µs

6

Set-up time for a repeated START condition

tSU;STA

0.6

－

µs

7

Data hold time

tHD;DAT

300*

－

ns

8

Data set-up time

tSU;DAT

300*

－

ns

9

Set-up time for STOP condition

tSU;STO

0.6

－

µs

All values referred to VIH min and VIL max levels (see Table 2).

*About 7(tHD;DAT), 8(tSU;DAT), make it the setup which a margin is fully in .

Table 2. Characteristics of the SDA and SCL I/O stages for I

2C-BUS devices

Parameter

Symbol

Fast-mode

Unit

Min.

Max.

10

LOW level input voltage:

VIL

-0.3

1

V

11

HIGH level input voltage:

VIH

2.3

5

V

12

Pulse width of spikes which must be suppressed by the input filter.

tSP

0

50

ns

13

LOW level output voltage (open drain or open collector): at 3mA sink

current.

VOL1

0

0.4

V

14

Input current in each I/O pin with an input voltage between 0.4V and

4.5V.

Ii

-10

10

µA

SDA

S

SCL

t

LOW

t

R

t

HD; DAT

P

t

HD; ST A

t

HIG H

t

B UF

t

F

t

SU; DAT

t

SU;STA

t

SU;STO

T

t

SP

t

HD; ST A

Sr

P

Figure 13. A command timing example in the I

2C data transmission.

SCL clock frequency:250kHz

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