DATA SHEET

1360MHz Dual Output LVPECL

Clock Synthesizer

8V43FS92432

8V43FS92432 REVISION 1 10/28/15

1

©2015 INTEGRATED DEVICE TECHNOLOGY, INC.

General Description

The 8V43FS92432 is a 3.3V-compatible, PLL based clock

synthesizer targeted for high performance clock generation in

mid-range to high-performance telecom, networking, and computing

applications. With output frequencies from 21.25MHz to 1360MHz

and the support of two differential PECL output signals, the device

meets the needs of the most demanding clock applications.

The 8V43FS92432 is a programmable high-frequency clock source

(clock synthesizer). The internal PLL generates a high-frequency

output signal based on a low-frequency reference signal. The

frequency of the output signal is programmable and can be changed

on the fly for frequency margining purpose.

The internal crystal oscillator uses the external quartz crystal as the

basis of its frequency reference. Alternatively, a LVCMOS compatible

clock signal can be used as a PLL reference signal. The frequency of

the internal crystal oscillator is divided by a selectable divider and

then multiplied by the PLL. Its output is scaled by a divider that is

M, and the PLL post-divider N determine the output frequency. The

feedback path of the PLL is internal.

parallel interfaces, and can provide one of six division ratios (2, 4, 8,

16, 32, 64). This divider extends the performance of the part while

are differential and are capable of driving a pair of transmission lines

terminated 50

 to V

internal PLL is separated from the power supply for the core logic

and output drivers to minimize noise induced jitter.

parallel interface uses the values at the M[9:0], NA[2:0], NB, and P

parallel inputs to configure the internal PLL dividers. The parallel

to the internal PLL configuration registers. The lock state of the PLL

is indicated by the LVCMOS-compatible LOCK output.

Features

parallel interface

Applications

telecommunication systems