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8V97053LNLGI8 数据表(PDF) 9 Page - Integrated Device Technology

部件名 8V97053LNLGI8
功能描述  Low Power Wideband Fractional RF Synthesizer / PLL
Download  68 Pages
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制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

8V97053LNLGI8 数据表(HTML) 9 Page - Integrated Device Technology

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©2016 Integrated Device Technology, Inc.
August 18, 2016
8V97053L Datasheet
Principles of Operation
Synthesizer Programming
The Fractional-N architecture is implemented via a cascaded programmable dual modulus prescaler. The N divider offers a division ratio in the
feedback path of the PLL, and is given by programming the value of INT, FRAC and MOD in the following equation:
N = INT + FRAC/MOD
(1)
INT is the divide ratio of the binary 16-bits counter (refer to Table 5B, Page 22).
FRAC is the numerator value of the fractional divide ratio. It is programmable from 0 to (MOD – 1). Refer to Table 5C when in 12-bit mode, or
Table 12K when in 16-bit mode.
MOD is the 12-bit or 16-bit modulus. It is programmable from 2 to 4095 in 12-bit mode, and 2 to 65535 in 16-bit mode. Refer to Table 6D when
in 12-bit mode, or Table 12J when in 16-bit mode.
The VCO frequency (fVCO) at RF_OUTA or RF_OUTB is given by the following equation:
fVCO = fPFD x (INT + FRAC/MOD)
(2)
fPFD is the frequency at the input of the Phase and Frequency Detector (PFD).
The 8V97053L offers an Integer mode. To enable that mode, the user has to program the FRAC value to 0.
The device’s VCO features three VCO band-splits to cover the entire range with sufficient margin for process, voltage, and temperature
variations. These are automatically selected by invoking the Autocal feature. The charge pump current is also programmable via the ICP
SETTING register for maximum flexibility.
Via Register 4, one can enable RF_OUTA or both outputs. Similarly, one can disable RF_OUTB or both outputs.
Reference Input Stage
The 8V97053L features one single-ended reference clock input (REF_IN). This single-ended input can be driven by an ac-coupled sine wave
or square wave.
In Power Down mode this input is set to High-Impedance to prevent loading of the reference source.The reference input signal path also
includes an optional doubler.


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