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9ZXL1530BKLFT 数据表(PDF) 3 Page - Integrated Device Technology

部件名 9ZXL1530BKLFT
功能描述  15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
Download  19 Pages
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制造商  IDT [Integrated Device Technology]
网页  http://www.idt.com
标志 IDT - Integrated Device Technology

9ZXL1530BKLFT 数据表(HTML) 3 Page - Integrated Device Technology

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9ZXL1530
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
IDT®
15-OUTPUT DB1900Z LOW-POWER DERIVATIVE
3
9ZXL1530
REV D 112015
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
1
VDDA
PWR
3.3V power for the PLL core.
2
GNDA
PWR
Ground pin for the PLL core.
3
100M_133M#
IN
3.3V Input to select operating frequency
See Functionality Table for Definition
4
HIBW_BYPM_LOBW#
IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for D etails.
5CKPWRGD_PD#
IN
N otifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on
subsequent assertions. Low enters Power D own Mode.
6
GND
PWR
Ground pin.
7VDDR
PWR
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
filtered appropriately.
8
DIF_IN
IN
0.7 V Differential TRUE input
9
DIF_IN#
IN
0.7 V Differential Complementary Input
10
SMB_A0_tri
IN
SMBus address bit. This is a tri-level input that w orks in conjunction with the SMB_A1 to decode 1 of 9 SMBus
Addresses.
11
SMBDAT
I/O
D ata pin of SMBUS circuitry, 5V tolerant
12
SMBCLK
IN
C lock pin of SMBU S circuitry, 5V tolerant
13
SMB_A1_tri
IN
SMBus address bit. This is a tri-level input that w orks in conjunction with the SMB_A0 to decode 1 of 9 SMBus
Addresses.
14
FBOU T_NC#
OU T
C omplementary half of differential feedback output. This pin should NOT be connected to anything outside the
chip. It exists to provide delay path matching to get 0 propagation delay.
15
FBOU T_NC
OU T
True half of differential feedback output. This pin should NOT be connected to anything outside the chip. It
exists to provide delay path matching to get 0 propagation delay.
16
GND
PWR
Ground pin.
17
DIF_0
OU T
0.7V differential true clock output
18
DIF_0#
OU T
0.7V differential Complementary clock output
19
VDDIO
PWR
Power supply for differential outputs
20
GND
PWR
Ground pin.
21
DIF_1
OU T
0.7V differential true clock output
22
DIF_1#
OU T
0.7V differential Complementary clock output
23
DIF_2
OU T
0.7V differential true clock output
24
DIF_2#
OU T
0.7V differential Complementary clock output
25
GND
PWR
Ground pin.
26
VDD
PWR
Power supply, nominal 3.3V
27
DIF_3
OU T
0.7V differential true clock output
28
DIF_3#
OU T
0.7V differential Complementary clock output
29
DIF_4
OU T
0.7V differential true clock output
30
DIF_4#
OU T
0.7V differential Complementary clock output
31
VDDIO
PWR
Power supply for differential outputs
32
GND
PWR
Ground pin.


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