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MC74VHCT240ADTRG 数据表(PDF) 1 Page - ON Semiconductor

部件名 MC74VHCT240ADTRG
功能描述  Octal Bus Buffer/Line Driver
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

MC74VHCT240ADTRG 数据表(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 7
1
Publication Order Number:
MC74VHCT240A/D
MC74VHCT240A
Octal Bus Buffer/Line Driver
Inverting with 3−State Outputs
The MC74VHCT240A is an advanced high speed CMOS octal bus
buffer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHCT240A is an inverting 3−state buffer, and has two
active−low output enables. This device is designed to be used with
3−state memory address drivers, etc.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
The VHCT240A input and output (when disabled) structures
provide protection when voltages between 0 V and 5.5 V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply
voltage−input/output voltage mismatch, battery backup, hot insertion,
etc.
Features
High Speed: tPD = 5.6 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Designed for 4.5 V to 5.5 V Operating Range
Low Noise: VOLP = 1.1 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 110 FETs or 27.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
20
1
TSSOP−20
SUFFIX DT
CASE 948E
SOIC−20WB
SUFFIX DW
CASE 751D
VHCT
240A
ALYW
G
G
1
1
20
1
VHCT240A
AWLYYWWG
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W
= Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)


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