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BD26503GUL-E2 数据表(PDF) 11 Page - Rohm |
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BD26503GUL-E2 数据表(HTML) 11 Page - Rohm |
11 / 44 page Technical Note 11/40 BD26503GUL www.rohm.com 2013.02 - Rev.A © 2013 ROHM Co., Ltd. All rights reserved. 2. I 2C BUS format When IFMODE is set to “L”, it can interface with I 2C BUS format. (1) Slave address CE A7 A6 A5 A4 A3 A2 A1 R/W L 1 1 1 0 1 0 0 0 H 1 1 1 0 1 0 1 (2) Bit Transfer SCL transfers 1-bit data during H. During H of SCL, SDA cannot be changed at the time of bit transfer. If SDA changes while SCL is H, START conditions or STOP conditions will occur and it will be interpreted as a control signal. SDA SCL SDA a state of stability : Data are effective SDA It can change Fig.6 Bit transfer (I 2C format) (3) START and STOP condition When SDA and SCL are H, data is not transferred on the I 2C- bus. This condition indicates, if SDA changes from H to L while SCL has been H, it will become START (S) conditions, and an access start, if SDA changes from L to H while SCL has been H, it will become STOP (P) conditions and an access end. SDA SCL S P START condition STOP condition Fig.7 START/STOP condition (I 2C format) (4) Acknowledge It transfers data 8 bits each after the occurrence of START condition. A transmitter opens SDA after transfer 8bits data, and a receiver returns the acknowledge signal by setting SDA to L. 12 8 9 DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER acknowledge not acknowledge S START condition clock pulse for acknowledgement SCL Fig.8 Acknowledge (I 2C format) |
类似零件编号 - BD26503GUL-E2 |
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类似说明 - BD26503GUL-E2 |
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